Simulation Results: hmac

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.70 %
  • code
  • 97.80 %
  • assert
  • 97.60 %
  • func
  • 43.69 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.960s 1442.953us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.790s 50.434us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.920s 28.480us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.440s 482.641us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.100s 591.763us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.940s 48.041us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.920s 28.480us 1 1 100.00
hmac_csr_aliasing 5.100s 591.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 61.760s 30632.082us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 37.780s 5206.929us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 209.580s 19890.302us 1 1 100.00
hmac_test_sha384_vectors 20.130s 1425.208us 1 1 100.00
hmac_test_sha512_vectors 21.420s 1389.500us 1 1 100.00
hmac_test_hmac256_vectors 12.190s 438.141us 1 1 100.00
hmac_test_hmac384_vectors 10.380s 875.498us 1 1 100.00
hmac_test_hmac512_vectors 8.880s 1126.700us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 17.970s 12246.235us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 199.230s 2429.491us 1 1 100.00
error 1 1 100.00
hmac_error 109.880s 14140.673us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 39.850s 7977.043us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.960s 1442.953us 1 1 100.00
hmac_long_msg 61.760s 30632.082us 1 1 100.00
hmac_back_pressure 37.780s 5206.929us 1 1 100.00
hmac_datapath_stress 199.230s 2429.491us 1 1 100.00
hmac_burst_wr 17.970s 12246.235us 1 1 100.00
hmac_stress_all 1191.150s 272651.567us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.960s 1442.953us 1 1 100.00
hmac_long_msg 61.760s 30632.082us 1 1 100.00
hmac_back_pressure 37.780s 5206.929us 1 1 100.00
hmac_datapath_stress 199.230s 2429.491us 1 1 100.00
hmac_wipe_secret 39.850s 7977.043us 1 1 100.00
hmac_test_sha256_vectors 209.580s 19890.302us 1 1 100.00
hmac_test_sha384_vectors 20.130s 1425.208us 1 1 100.00
hmac_test_sha512_vectors 21.420s 1389.500us 1 1 100.00
hmac_test_hmac256_vectors 12.190s 438.141us 1 1 100.00
hmac_test_hmac384_vectors 10.380s 875.498us 1 1 100.00
hmac_test_hmac512_vectors 8.880s 1126.700us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.960s 1442.953us 1 1 100.00
hmac_long_msg 61.760s 30632.082us 1 1 100.00
hmac_back_pressure 37.780s 5206.929us 1 1 100.00
hmac_datapath_stress 199.230s 2429.491us 1 1 100.00
hmac_burst_wr 17.970s 12246.235us 1 1 100.00
hmac_error 109.880s 14140.673us 1 1 100.00
hmac_wipe_secret 39.850s 7977.043us 1 1 100.00
hmac_test_sha256_vectors 209.580s 19890.302us 1 1 100.00
hmac_test_sha384_vectors 20.130s 1425.208us 1 1 100.00
hmac_test_sha512_vectors 21.420s 1389.500us 1 1 100.00
hmac_test_hmac256_vectors 12.190s 438.141us 1 1 100.00
hmac_test_hmac384_vectors 10.380s 875.498us 1 1 100.00
hmac_test_hmac512_vectors 8.880s 1126.700us 1 1 100.00
hmac_stress_all 1191.150s 272651.567us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1191.150s 272651.567us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.590s 19.902us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.620s 29.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.330s 31.555us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.330s 31.555us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.790s 50.434us 1 1 100.00
hmac_csr_rw 0.920s 28.480us 1 1 100.00
hmac_csr_aliasing 5.100s 591.763us 1 1 100.00
hmac_same_csr_outstanding 1.590s 469.988us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.790s 50.434us 1 1 100.00
hmac_csr_rw 0.920s 28.480us 1 1 100.00
hmac_csr_aliasing 5.100s 591.763us 1 1 100.00
hmac_same_csr_outstanding 1.590s 469.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.970s 76.449us 1 1 100.00
hmac_tl_intg_err 2.760s 418.269us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.760s 418.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.960s 1442.953us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.910s 76.308us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 95.750s 19956.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.850s 29.078us 1 1 100.00