Simulation Results

Simulation Results: i2c

16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.11 %

code
78.85 %

assert
97.25 %

func
82.24 %

line
96.60 %

branch
92.69 %

cond
87.41 %

toggle
73.52 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	19.420s	36318.364us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.850s	4105.778us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.720s	160.043us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.920s	87.917us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.420s	223.847us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.300s	492.339us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.750s	37.712us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.920s	87.917us	1	1	100.00
	i2c_csr_aliasing	1.300s	492.339us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	1.030s	624.061us	1	1	100.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	542.460s	106526.440us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	911.170s	50490.968us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.860s	33.050us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	143.900s	17969.764us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	50.230s	1595.241us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.890s	167.297us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.880s	1038.599us	1	1	100.00
	i2c_host_fifo_reset_rx	2.620s	172.068us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	101.200s	15764.903us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	7.020s	2682.286us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.300s	150.860us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.220s	2467.702us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	315.100s	64575.421us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.150s	2177.543us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	46.750s	1518.941us	1	1	100.00
	i2c_target_intr_smoke	5.120s	1323.579us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.170s	707.327us	1	1	100.00
	i2c_target_fifo_reset_tx	0.930s	135.335us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	18.290s	29958.567us	1	1	100.00
	i2c_target_stress_rd	46.750s	1518.941us	1	1	100.00
	i2c_target_intr_stress_wr	110.650s	12691.130us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.690s	1050.891us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	25.700s	5241.750us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.070s	1488.581us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.310s	4599.403us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.710s	456.716us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.930s	176.249us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	911.170s	50490.968us	1	1	100.00
	i2c_host_perf_precise	21.710s	2289.769us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	7.020s	2682.286us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.220s	96.538us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	1.840s	4987.550us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.730s	506.993us	1	1	100.00
	i2c_target_nack_txstretch	1.230s	188.172us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.690s	1419.914us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.320s	494.490us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.810s	55.873us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.650s	27.243us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.290s	304.192us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.290s	304.192us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.720s	160.043us	1	1	100.00
	i2c_csr_rw	0.920s	87.917us	1	1	100.00
	i2c_csr_aliasing	1.300s	492.339us	1	1	100.00
	i2c_same_csr_outstanding	0.890s	155.158us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.720s	160.043us	1	1	100.00
	i2c_csr_rw	0.920s	87.917us	1	1	100.00
	i2c_csr_aliasing	1.300s	492.339us	1	1	100.00
	i2c_same_csr_outstanding	0.890s	155.158us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.290s	145.799us	1	1	100.00
	i2c_sec_cm	0.960s	79.551us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.290s	145.799us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	17.960s	1018.592us	1
target_error_intr				1
	i2c_target_unexp_stop	1.040s	89.692us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	1.670s	65.316us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	10434995492054083356449151219430763895357151763273245928530700309126228020147	84	UVM_INFO @ 2467701862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	56338912902115870031814806550523710971045637382547759232911204977528932830568	78	UVM_INFO @ 89691816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!				1 test run
	i2c_target_stress_all	77003213978515039973462450908190225134781879447127171066032922224922117280755	97	UVM_INFO @ 64575421256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	114489043128414627610269777089850077968291529753080192577445298349054279001404	109	UVM_INFO @ 1018591959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_target_stress_all_with_rand_reset	29283172962933897422755054294602438465705407829599902723896468615213055924064	96	UVM_INFO @ 65315827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	75292386874210590333845388368294556672999449957433001930692334896237174909699	78	UVM_INFO @ 188172334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---