Simulation Results: lc_ctrl/volatile_unlock_disabled

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.15 %
  • code
  • 84.36 %
  • assert
  • 94.97 %
  • func
  • 94.13 %
  • line
  • 97.15 %
  • branch
  • 93.56 %
  • cond
  • 79.86 %
  • toggle
  • 86.73 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.050s 47.129us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.250s 72.242us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.030s 16.839us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.410s 173.253us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 66.296us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.680s 47.534us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.030s 16.839us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 66.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.720s 116.415us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.400s 2299.590us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.070s 47.538us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.460s 134.163us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.410s 566.127us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_prog_failure 2.460s 134.163us 1 1 100.00
lc_ctrl_errors 9.410s 566.127us 1 1 100.00
lc_ctrl_security_escalation 5.810s 250.516us 1 1 100.00
lc_ctrl_jtag_state_failure 20.380s 1813.111us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.930s 79.592us 1 1 100.00
lc_ctrl_jtag_errors 25.880s 11132.454us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.990s 221.490us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.450s 1278.203us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.930s 79.592us 1 1 100.00
lc_ctrl_jtag_errors 25.880s 11132.454us 1 1 100.00
lc_ctrl_jtag_access 1.900s 152.937us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.690s 732.962us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.580s 46.305us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.640s 138.167us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.730s 7045.227us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.480s 1557.091us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.360s 196.965us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.540s 101.338us 1 1 100.00
lc_ctrl_jtag_alert_test 1.030s 54.962us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.220s 1975.454us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 15.546us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 30.200s 5144.595us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.070s 32.354us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.470s 424.746us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.470s 424.746us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.250s 72.242us 1 1 100.00
lc_ctrl_csr_rw 1.030s 16.839us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 66.296us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 29.301us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.250s 72.242us 1 1 100.00
lc_ctrl_csr_rw 1.030s 16.839us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 66.296us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 29.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
lc_ctrl_tl_intg_err 2.290s 80.904us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.290s 80.904us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.400s 2299.590us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.850s 309.726us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1312.304us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.810s 250.516us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.720s 116.415us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.450s 1278.203us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.600s 221.795us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.600s 221.795us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.870s 912.198us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.230s 7857.389us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.230s 7857.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 38.170s 21448.577us 1 1 100.00