Simulation Results: lc_ctrl/volatile_unlock_enabled

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.71 %
  • code
  • 83.80 %
  • assert
  • 94.55 %
  • func
  • 93.77 %
  • line
  • 97.04 %
  • branch
  • 93.37 %
  • cond
  • 79.13 %
  • toggle
  • 86.85 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.560s 30.757us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.930s 188.958us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.870s 199.436us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.440s 68.489us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.680s 160.217us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.470s 95.640us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.870s 199.436us 1 1 100.00
lc_ctrl_csr_aliasing 1.680s 160.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.250s 74.171us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.290s 397.173us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.950s 106.568us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.570s 20.691us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.710s 318.495us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_prog_failure 1.570s 20.691us 1 1 100.00
lc_ctrl_errors 4.710s 318.495us 1 1 100.00
lc_ctrl_security_escalation 5.760s 3508.794us 1 1 100.00
lc_ctrl_jtag_state_failure 24.000s 3888.776us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.170s 1588.398us 1 1 100.00
lc_ctrl_jtag_errors 22.190s 2304.381us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.600s 619.805us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.150s 307.730us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.170s 1588.398us 1 1 100.00
lc_ctrl_jtag_errors 22.190s 2304.381us 1 1 100.00
lc_ctrl_jtag_access 6.610s 2835.894us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.690s 4663.161us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.270s 360.495us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.040s 169.605us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.190s 1809.504us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.190s 5510.067us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.230s 26.670us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.590s 509.630us 1 1 100.00
lc_ctrl_jtag_alert_test 1.470s 222.359us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.110s 370.760us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.960s 17.780us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 166.820s 26494.780us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.300s 36.470us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.640s 54.052us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.640s 54.052us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 188.958us 1 1 100.00
lc_ctrl_csr_rw 0.870s 199.436us 1 1 100.00
lc_ctrl_csr_aliasing 1.680s 160.217us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.950s 116.388us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 188.958us 1 1 100.00
lc_ctrl_csr_rw 0.870s 199.436us 1 1 100.00
lc_ctrl_csr_aliasing 1.680s 160.217us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.950s 116.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
lc_ctrl_tl_intg_err 1.920s 477.322us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.920s 477.322us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.290s 397.173us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.600s 1147.209us 1 1 100.00
lc_ctrl_sec_cm 6.320s 253.481us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.760s 3508.794us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.250s 74.171us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.150s 307.730us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 14.180s 692.739us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 14.180s 692.739us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.140s 1877.011us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.860s 1597.558us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.860s 1597.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.410s 306.425us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 60654237491705849664778235318470294841029499887515979357388409697939610290120 953
UVM_INFO @ 306424863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---