Simulation Results: otbn

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.74 %
  • code
  • 81.92 %
  • assert
  • 89.84 %
  • func
  • 97.46 %
  • block
  • 97.75 %
  • line
  • 97.94 %
  • branch
  • 81.85 %
  • toggle
  • 81.69 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 39.276us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 28.000s 14.278us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 28.000s 16.068us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 29.000s 77.750us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 30.000s 19.655us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 30.000s 102.983us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 28.000s 16.068us 1 1 100.00
otbn_csr_aliasing 30.000s 19.655us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 71.000s 3367.758us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 30.000s 1747.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 31.000s 387.994us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 49.000s 667.702us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 72.000s 438.573us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 38.000s 154.508us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 23.000s 20.846us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 24.123us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 11.000s 243.754us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 31.000s 18.518us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 17.000s 14.415us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 143.078us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 143.078us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 28.000s 14.278us 1 1 100.00
otbn_csr_rw 28.000s 16.068us 1 1 100.00
otbn_csr_aliasing 30.000s 19.655us 1 1 100.00
otbn_same_csr_outstanding 5.000s 81.726us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 28.000s 14.278us 1 1 100.00
otbn_csr_rw 28.000s 16.068us 1 1 100.00
otbn_csr_aliasing 30.000s 19.655us 1 1 100.00
otbn_same_csr_outstanding 5.000s 81.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 22.000s 50.468us 1 1 100.00
otbn_dmem_err 30.000s 22.131us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 33.000s 60.263us 1 1 100.00
otbn_controller_ispr_rdata_err 33.000s 235.981us 1 1 100.00
otbn_mac_bignum_acc_err 24.000s 63.995us 1 1 100.00
otbn_urnd_err 8.000s 18.274us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 22.000s 20.460us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 10.000s 52.495us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 11.296us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
otbn_tl_intg_err 20.000s 121.338us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 45.000s 807.987us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 39.276us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 30.000s 22.131us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 22.000s 50.468us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 20.000s 121.338us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 23.000s 20.846us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 22.000s 50.468us 1 1 100.00
otbn_dmem_err 30.000s 22.131us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 24.123us 1 1 100.00
otbn_illegal_mem_acc 22.000s 20.460us 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 22.000s 50.468us 1 1 100.00
otbn_dmem_err 30.000s 22.131us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 24.123us 1 1 100.00
otbn_illegal_mem_acc 22.000s 20.460us 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 23.000s 20.846us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 22.000s 50.468us 1 1 100.00
otbn_dmem_err 30.000s 22.131us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 24.123us 1 1 100.00
otbn_illegal_mem_acc 22.000s 20.460us 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 30.000s 18.195us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 94.483us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 26.000s 279.365us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 26.000s 279.365us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 129.242us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 51.014us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 9.000s 322.733us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 9.000s 322.733us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 8.000s 21.542us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 72.000s 438.573us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 25.648us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 147.219us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 173.000s 834.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 91.000s 418.157us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 46.235us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 81268505648920088848152570283007427882721729090901885150668579915776798150227 412
UVM_INFO @ 667702330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 69169375636190883145245043837888044378894068331341627255241490050494991380356 224
UVM_INFO @ 418157444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 22839013852037595658330365175890983839411371879650711102002029838356859900354 129
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 322733402 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 322733402 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 322733402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---