Simulation Results: otp_ctrl

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.25 %
  • code
  • 79.01 %
  • assert
  • 92.65 %
  • func
  • 75.09 %
  • line
  • 88.40 %
  • branch
  • 82.18 %
  • cond
  • 90.05 %
  • toggle
  • 88.39 %
  • FSM
  • 46.01 %
Validation stages
V1
88.89%
V2
100.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.630s 213.440us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.890s 272.466us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.740s 1582.986us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.550s 81.707us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.870s 1646.357us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 8.710s 3170.025us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.110s 53.680us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.550s 81.707us 1 1 100.00
otp_ctrl_csr_aliasing 8.710s 3170.025us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.190s 38.968us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.260s 74.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.410s 6015.787us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.560s 176.420us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 6.240s 300.318us 1 1 100.00
otp_ctrl_check_fail 19.240s 1679.984us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 8.400s 4688.869us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 38.250s 15567.984us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.820s 670.282us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 6.980s 654.478us 1 1 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.510s 1606.225us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 9.490s 2089.071us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 17.910s 905.117us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 89.820s 10774.024us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.270s 44.698us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.750s 111.211us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.310s 152.227us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.310s 152.227us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.740s 1582.986us 1 1 100.00
otp_ctrl_csr_rw 1.550s 81.707us 1 1 100.00
otp_ctrl_csr_aliasing 8.710s 3170.025us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.950s 139.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.740s 1582.986us 1 1 100.00
otp_ctrl_csr_rw 1.550s 81.707us 1 1 100.00
otp_ctrl_csr_aliasing 8.710s 3170.025us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.950s 139.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
otp_ctrl_tl_intg_err 20.820s 19252.180us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 20.820s 19252.180us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.890s 272.466us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.890s 272.466us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
otp_ctrl_macro_errs 9.490s 2089.071us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
otp_ctrl_macro_errs 9.490s 2089.071us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 18.260s 3961.623us 1 1 100.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.560s 176.420us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 19.240s 1679.984us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 38.250s 15567.984us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 38.250s 15567.984us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 38.250s 15567.984us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 38.250s 15567.984us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 38.250s 15567.984us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.890s 272.466us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 38.250s 15567.984us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.890s 272.466us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 46.660s 10245.013us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 8.400s 4688.869us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.890s 272.466us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.890s 272.466us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 9.490s 2089.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.140s 3959.938us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 3.940s 277.132us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 71412052096047943109947716847613852800783774404114324689658177941636695519964 1582
UVM_INFO @ 277131685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_sec_cm 102626940487887106314972435973780157610299012308009104166442966384715630333432 123
UVM_INFO @ 10245012735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 87154059079718605519220723957212202904657950429420516006193525280324147549676 92
UVM_INFO @ 53679820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---