Simulation Results: pwrmgr

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.11 %
  • code
  • 97.34 %
  • assert
  • 98.96 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.62 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.630s 48.620us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.670s 64.264us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.830s 45.026us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.420s 552.118us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.980s 24.940us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.870s 36.504us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.830s 45.026us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 24.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.870s 244.795us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.870s 244.795us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.780s 34.787us 1 1 100.00
pwrmgr_lowpower_invalid 0.670s 44.431us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 2.270s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.760s 161.259us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.270s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.340s 358.621us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.790s 308.414us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 2.300s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 2.110s 2497.728us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.630s 34.646us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.200s 99.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.200s 99.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 64.264us 1 1 100.00
pwrmgr_csr_rw 0.830s 45.026us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 24.940us 1 1 100.00
pwrmgr_same_csr_outstanding 0.770s 27.985us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 64.264us 1 1 100.00
pwrmgr_csr_rw 0.830s 45.026us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 24.940us 1 1 100.00
pwrmgr_same_csr_outstanding 0.770s 27.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.410s 293.544us 1 1 100.00
pwrmgr_sec_cm 1.570s 679.973us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.570s 679.973us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.570s 679.973us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.410s 293.544us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.930s 759.152us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.340s 358.621us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.600s 1126.948us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.830s 76.345us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.630s 78.334us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.570s 679.973us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.570s 679.973us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.570s 679.973us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.670s 49.173us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.730s 85.529us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.880s 362.212us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.830s 45.026us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.830s 45.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.860s 357.627us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 9.400s 4834.257us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
pwrmgr_reset 23095809114407916993731999666697352670794638428403610383184386928959350965671 130
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 41719329023219125598877927125381826817099951665791313451258516051050381772688 89
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---