Simulation Results: rom_ctrl/64kb

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.02 %
  • code
  • 96.83 %
  • assert
  • 97.10 %
  • func
  • 97.14 %
  • line
  • 99.33 %
  • branch
  • 98.91 %
  • cond
  • 97.62 %
  • toggle
  • 94.97 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.910s 1758.554us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.960s 218.247us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.680s 286.754us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.450s 2047.625us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.330s 3560.815us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.610s 210.310us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.680s 286.754us 1 1 100.00
rom_ctrl_csr_aliasing 6.330s 3560.815us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.250s 2515.517us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.840s 212.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.320s 168.974us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 32.290s 4611.556us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.870s 2396.306us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.600s 1936.150us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.660s 554.955us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.660s 554.955us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.960s 218.247us 1 1 100.00
rom_ctrl_csr_rw 7.680s 286.754us 1 1 100.00
rom_ctrl_csr_aliasing 6.330s 3560.815us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.680s 545.596us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.960s 218.247us 1 1 100.00
rom_ctrl_csr_rw 7.680s 286.754us 1 1 100.00
rom_ctrl_csr_aliasing 6.330s 3560.815us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.680s 545.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 49.790s 18609.404us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 260.170s 1847.260us 1 1 100.00
rom_ctrl_tl_intg_err 53.170s 1309.882us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 260.170s 1847.260us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 260.170s 1847.260us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 260.170s 1847.260us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 260.170s 1847.260us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.910s 1758.554us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.910s 1758.554us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.910s 1758.554us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 53.170s 1309.882us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
rom_ctrl_kmac_err_chk 13.870s 2396.306us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 150.360s 4428.772us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 49.790s 18609.404us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 260.170s 1847.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 61.990s 2470.252us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 72044387220091792169928078243013107933411735278941004233440840238641949668525 79
UVM_INFO @ 168973924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---