Simulation Results: rstmgr

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.53 %
  • code
  • 99.31 %
  • assert
  • 98.53 %
  • func
  • 97.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.370s 139.369us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.140s 148.373us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.870s 80.947us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.120s 1271.213us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.170s 440.193us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.300s 173.202us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.870s 80.947us 1 1 100.00
rstmgr_csr_aliasing 2.170s 440.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.880s 169.957us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.490s 173.076us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.980s 197.331us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 2.970s 873.031us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 2.970s 873.031us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 2.970s 873.031us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 2.970s 873.031us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 32.570s 14753.224us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.830s 67.940us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.890s 488.126us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.890s 488.126us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.140s 148.373us 1 1 100.00
rstmgr_csr_rw 0.870s 80.947us 1 1 100.00
rstmgr_csr_aliasing 2.170s 440.193us 1 1 100.00
rstmgr_same_csr_outstanding 1.160s 138.999us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.140s 148.373us 1 1 100.00
rstmgr_csr_rw 0.870s 80.947us 1 1 100.00
rstmgr_csr_aliasing 2.170s 440.193us 1 1 100.00
rstmgr_same_csr_outstanding 1.160s 138.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.080s 17870.253us 1 1 100.00
rstmgr_tl_intg_err 2.500s 950.874us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.080s 17870.253us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.080s 17870.253us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.500s 950.874us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.920s 114.482us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.320s 1411.996us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.140s 301.942us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.080s 17870.253us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 80.947us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 80.947us 1 1 100.00