Simulation Results: rv_timer

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.62 %
  • code
  • 100.00 %
  • assert
  • 98.73 %
  • func
  • 94.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.630s 77.364us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.570s 147.506us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 253.237us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.420s 249.031us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.860s 140.339us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.710s 67.193us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 253.237us 1 1 100.00
rv_timer_csr_aliasing 0.860s 140.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.680s 548.925us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.000s 2359.162us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 372.140s 530159.450us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 372.140s 530159.450us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.500s 6253.983us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.550s 13.230us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.580s 12.773us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.300s 91.823us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.300s 91.823us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 147.506us 1 1 100.00
rv_timer_csr_rw 0.560s 253.237us 1 1 100.00
rv_timer_csr_aliasing 0.860s 140.339us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 73.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 147.506us 1 1 100.00
rv_timer_csr_rw 0.560s 253.237us 1 1 100.00
rv_timer_csr_aliasing 0.860s 140.339us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 73.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.980s 1394.305us 1 1 100.00
rv_timer_tl_intg_err 1.190s 157.714us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.190s 157.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.580s 60.636us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 85.012us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 20.380s 3080.028us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 91154322638425208344655457202292281172507083000428370682018901200745461374366 75
UVM_INFO @ 60635606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 107956305842654439760444030687639632630373852768878841914540511720649764143517 75
UVM_INFO @ 548924966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 39046041689338456731911983495602771266224297190042248348842859168337842175567 75
UVM_INFO @ 85012114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---