Simulation Results: spi_device/1r1w

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.52 %
  • code
  • 91.27 %
  • assert
  • 95.40 %
  • func
  • 63.89 %
  • line
  • 98.87 %
  • branch
  • 98.16 %
  • cond
  • 96.13 %
  • toggle
  • 73.83 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 1.670s 109.616us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.290s 62.724us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.100s 17.705us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 20.140s 5522.371us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 17.390s 1291.361us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.340s 193.334us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.100s 17.705us 1 1 100.00
spi_device_csr_aliasing 17.390s 1291.361us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.980s 49.322us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.420s 38.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.700s 20.278us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.850s 2.092us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.670s 3.581us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.010s 320.786us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.010s 320.786us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.340s 502.477us 1 1 100.00
spi_device_tpm_sts_read 0.660s 24.500us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 16.760s 18113.912us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.960s 2173.023us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.880s 91.948us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.880s 91.948us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.440s 769.923us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.440s 769.923us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.440s 769.923us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.440s 769.923us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.440s 769.923us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.830s 615.663us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 33.940s 5639.726us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 33.940s 5639.726us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 33.940s 5639.726us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 17.360s 3635.038us 1 1 100.00
spi_device_read_buffer_direct 8.340s 1600.617us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 33.940s 5639.726us 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 27.780s 9703.967us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.020s 1668.943us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.020s 1668.943us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 17.980s 25448.152us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 1.670s 109.616us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 17.200s 1534.339us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 84.220s 11532.497us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.770s 12.704us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.750s 38.945us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.300s 762.293us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.300s 762.293us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.290s 62.724us 1 1 100.00
spi_device_csr_rw 1.100s 17.705us 1 1 100.00
spi_device_csr_aliasing 17.390s 1291.361us 1 1 100.00
spi_device_same_csr_outstanding 2.400s 279.493us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.290s 62.724us 1 1 100.00
spi_device_csr_rw 1.100s 17.705us 1 1 100.00
spi_device_csr_aliasing 17.390s 1291.361us 1 1 100.00
spi_device_same_csr_outstanding 2.400s 279.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.450s 323.560us 1 1 100.00
spi_device_tl_intg_err 11.590s 2513.371us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.590s 2513.371us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 78781335001778896413420739159611990406209528349954150968592469396908906271975 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1540994 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1540994 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[921])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 68801301654392336313899617420742272220447656587897578142814928474052823667754 76
UVM_ERROR @ 861855 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x172 [101110010] vs 0x0 [0])
UVM_ERROR @ 929855 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x47 [1000111] vs 0x0 [0])
UVM_ERROR @ 1028855 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7e [1111110] vs 0x0 [0])
UVM_ERROR @ 1102855 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x118 [100011000] vs 0x0 [0])