Simulation Results: sram_ctrl/main

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.05 %
  • code
  • 96.46 %
  • assert
  • 97.28 %
  • func
  • 94.40 %
  • block
  • 95.63 %
  • line
  • 96.38 %
  • branch
  • 93.37 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 693.540us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 14.150us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.780us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 757.630us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.710us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 5773.410us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 19.780us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.710us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 234.000s 26529.999us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 47.000s 6501.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 25.000s 25241.306us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 118.000s 3957.782us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 125.000s 23713.953us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 21.000s 5231.684us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 33.000s 41381.980us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 1482.065us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 695.338us 1 1 100.00
sram_ctrl_partial_access_b2b 159.000s 44105.493us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 2637.094us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 1399.862us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 4427.479us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 8191.382us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 356.159us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 281.000s 21363.390us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 35.588us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 121.667us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 121.667us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 14.150us 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.780us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.710us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.696us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 14.150us 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.780us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.710us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.696us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 7256.556us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 627.326us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 524.510us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 627.326us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 524.510us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 8191.382us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 8191.382us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.780us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1482.065us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1482.065us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1482.065us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 33.000s 41381.980us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 679.077us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 7256.556us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 693.724us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 693.540us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 693.540us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 1482.065us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 627.326us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 33.000s 41381.980us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 627.326us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 627.326us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 693.540us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 627.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.000s 265.859us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 17038693399582521665184852776111333335725128712869309199433073565090447220949 86
UVM_INFO @ 2637094291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 28243569568152995214111851559030522395559435484637374752864026316491896356745 86
UVM_INFO @ 1399861850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 3422215493904227894186404694187623674307519110751542750016871653193033796691 86
UVM_INFO @ 4427478601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---