Simulation Results: sram_ctrl/ret

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.38 %
  • code
  • 82.31 %
  • assert
  • 97.26 %
  • func
  • 94.57 %
  • block
  • 93.69 %
  • line
  • 94.91 %
  • branch
  • 89.36 %
  • toggle
  • 78.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 89.905us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.060us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.238us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 630.208us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 60.577us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 87.523us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 16.238us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 60.577us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 11.000s 16281.317us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 100.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 937.406us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 84.000s 1882.943us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 700.993us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 3690.401us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 476.610us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 8695.817us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 89.577us 1 1 100.00
sram_ctrl_partial_access_b2b 138.000s 22096.740us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 119.786us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 33.430us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 37.231us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 161.322us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 83.839us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 12.000s 1259.996us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 38.197us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 38.115us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 38.115us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.060us 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.238us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 60.577us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 22.622us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.060us 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.238us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 60.577us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 22.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 908.960us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1665.008us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 276.790us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1665.008us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 276.790us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 161.322us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 161.322us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.238us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 8695.817us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 8695.817us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 8695.817us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 476.610us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 239.519us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 908.960us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 71.936us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 89.905us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 89.905us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 8695.817us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1665.008us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 476.610us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1665.008us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1665.008us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 89.905us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1665.008us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 24.000s 10984.668us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 112112900678350226010921001554780433148470542961672774945169974499112476022904 86
UVM_INFO @ 119786184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 2122072755011185476409233261964775409341923013118159222792791024024878809858 86
UVM_INFO @ 33430082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 45989890449561290452568563527860027439533604494205935614950244245635279543221 86
UVM_INFO @ 37230886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---