Simulation Results: sysrst_ctrl

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.22 %
  • code
  • 92.46 %
  • assert
  • 92.24 %
  • func
  • 70.97 %
  • line
  • 96.91 %
  • branch
  • 97.14 %
  • cond
  • 94.54 %
  • toggle
  • 100.00 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.460s 2126.148us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.360s 2531.293us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 3.980s 2176.961us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.050s 2505.864us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.140s 6061.144us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.940s 2037.793us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 47.240s 25877.289us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.190s 2492.745us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.760s 2131.208us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.940s 2037.793us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.190s 2492.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 228.410s 142871.290us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 51.510s 112047.293us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.970s 3326.232us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.700s 4024.881us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.670s 2529.133us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.710s 2207.121us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 8.110s 4329.865us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.870s 2649.763us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.650s 6443.090us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 65.370s 40099.858us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 25.720s 15600.111us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.910s 2014.283us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.310s 2077.390us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.420s 2352.728us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.420s 2352.728us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.140s 6061.144us 1 1 100.00
sysrst_ctrl_csr_rw 3.940s 2037.793us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.190s 2492.745us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.350s 5026.918us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.140s 6061.144us 1 1 100.00
sysrst_ctrl_csr_rw 3.940s 2037.793us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.190s 2492.745us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.350s 5026.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 10.220s 22089.115us 1 1 100.00
sysrst_ctrl_tl_intg_err 39.700s 22245.169us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 39.700s 22245.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.660s 18176.329us 1 1 100.00