Simulation Results: uart

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.29 %
  • code
  • 96.59 %
  • assert
  • 98.56 %
  • func
  • 63.73 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.20 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.440s 250.899us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.670s 79.751us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.660s 43.354us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.460s 44.286us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.070s 99.301us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.860s 34.121us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.660s 43.354us 1 1 100.00
uart_csr_aliasing 1.070s 99.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 55.390s 121666.905us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.440s 250.899us 1 1 100.00
uart_tx_rx 55.390s 121666.905us 1 1 100.00
parity_error 2 2 100.00
uart_intr 12.930s 28125.977us 1 1 100.00
uart_rx_parity_err 17.950s 171201.184us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 55.390s 121666.905us 1 1 100.00
uart_intr 12.930s 28125.977us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 145.680s 93016.846us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 66.800s 76046.730us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 50.960s 155037.470us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 12.930s 28125.977us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 12.930s 28125.977us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 12.930s 28125.977us 1 1 100.00
perf 1 1 100.00
uart_perf 343.020s 13912.464us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.280s 11981.309us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.280s 11981.309us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.120s 2691.883us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.020s 32753.996us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.830s 1708.514us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 2.130s 2149.090us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 248.630s 106324.548us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 66.190s 185523.971us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.650s 16.745us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.620s 49.995us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.560s 100.744us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.560s 100.744us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.670s 79.751us 1 1 100.00
uart_csr_rw 0.660s 43.354us 1 1 100.00
uart_csr_aliasing 1.070s 99.301us 1 1 100.00
uart_same_csr_outstanding 1.010s 119.122us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.670s 79.751us 1 1 100.00
uart_csr_rw 0.660s 43.354us 1 1 100.00
uart_csr_aliasing 1.070s 99.301us 1 1 100.00
uart_same_csr_outstanding 1.010s 119.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.810s 112.688us 1 1 100.00
uart_tl_intg_err 1.000s 51.885us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 51.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 38.580s 10831.574us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 88174597900263047832664845753240341397815140584358081573757725723111561379388 75
UVM_ERROR @ 995763708 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1055379033 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 1060247160 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 1069477920 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1