Simulation Results

Simulation Results: adc_ctrl

20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.88 %

code
92.65 %

assert
91.90 %

func
13.09 %

line
97.97 %

branch
96.23 %

cond
85.53 %

toggle
99.76 %

FSM
83.78 %

Validation stages

V1		100.00%
V2		57.89%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	4.650s	5768.941us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.660s	843.030us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	0.910s	627.232us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	61.360s	26406.389us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	2.170s	842.235us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.040s	378.831us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	0.910s	627.232us	1	1	100.00
	adc_ctrl_csr_aliasing	2.170s	842.235us	1	1	100.00

11/19 passed

57.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	1.270s	467.161us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	0.740s	434.861us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	0.960s	430.478us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.700s	361.098us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.770s	519.653us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.750s	396.363us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	1.010s	330.103us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.610s	414.399us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	4.610s	2826.384us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	5.510s	22556.867us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	43.170s	97059.403us	1	1	100.00
stress_all				1	1	100.00
	adc_ctrl_stress_all	1.530s	1214.126us	1	1	100.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	0.610s	512.121us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	1.060s	361.234us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	1.410s	647.862us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	1.410s	647.862us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.660s	843.030us	1	1	100.00
	adc_ctrl_csr_rw	0.910s	627.232us	1	1	100.00
	adc_ctrl_csr_aliasing	2.170s	842.235us	1	1	100.00
	adc_ctrl_same_csr_outstanding	2.490s	4198.381us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.660s	843.030us	1	1	100.00
	adc_ctrl_csr_rw	0.910s	627.232us	1	1	100.00
	adc_ctrl_csr_aliasing	2.170s	842.235us	1	1	100.00
	adc_ctrl_same_csr_outstanding	2.490s	4198.381us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	6.350s	4224.836us	1	1	100.00
	adc_ctrl_tl_intg_err	12.730s	8119.599us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	12.730s	8119.599us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	adc_ctrl_stress_all_with_rand_reset	0.850s	1073.416us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	94158474120544728481650670782078937470261306540546352057585636180183274865054	386	UVM_INFO @ 467161324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	115742788577538201602013305937972721084500712238560569726285511659841895958647	386	UVM_INFO @ 434860574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	815997028733954646491389460087742589656583285244614571849267446595575756759	386	UVM_INFO @ 430477921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	109158786834481454143516780843013897007910700293925144892552132826534012834549	386	UVM_INFO @ 361098462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	56926939161504139597512361316230923973565103271550335495377900937731153025801	386	UVM_INFO @ 519653475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	6906840239956420251852321791483584478775690991936598104057722705341314121622	386	UVM_INFO @ 396363426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	32474847232220945836780765208435087948917799323651664923904703608701681747694	386	UVM_INFO @ 414398744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	59476063685381287313486423111690106073107735333168690848275736387467468398191	386	UVM_INFO @ 330102830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	51150167499694716062343345407943604897646588808647278801492278205454807713081	399	UVM_INFO @ 1073415772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---