Simulation Results: alert_handler

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.23 %
  • code
  • 90.17 %
  • assert
  • 97.93 %
  • func
  • 79.59 %
  • line
  • 99.66 %
  • branch
  • 98.47 %
  • cond
  • 92.04 %
  • toggle
  • 86.50 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 30.330s 1004.463us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.740s 65.675us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.580s 135.060us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 163.840s 12573.969us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 150.800s 22741.707us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.870s 118.485us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.580s 135.060us 1 1 100.00
alert_handler_csr_aliasing 150.800s 22741.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 11.580s 190.304us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 44.480s 1693.344us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 666.970s 55002.847us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 32.530s 3769.721us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 30.330s 1004.463us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 21.750s 647.248us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 14.030s 830.509us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 158.350s 24856.206us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1582.070s 184730.127us 1 1 100.00
alert_handler_lpg_stub_clk 927.920s 32122.510us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 106.880s 3366.548us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 11.050s 403.577us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.670s 360.613us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.220s 12.558us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 13.610s 315.489us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 13.610s 315.489us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.740s 65.675us 1 1 100.00
alert_handler_csr_rw 3.580s 135.060us 1 1 100.00
alert_handler_csr_aliasing 150.800s 22741.707us 1 1 100.00
alert_handler_same_csr_outstanding 12.370s 1110.398us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.740s 65.675us 1 1 100.00
alert_handler_csr_rw 3.580s 135.060us 1 1 100.00
alert_handler_csr_aliasing 150.800s 22741.707us 1 1 100.00
alert_handler_same_csr_outstanding 12.370s 1110.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 224.820s 70145.293us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 224.820s 70145.293us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 224.820s 70145.293us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 224.820s 70145.293us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 304.140s 25900.881us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
alert_handler_tl_intg_err 26.330s 657.212us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 26.330s 657.212us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 224.820s 70145.293us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 30.330s 1004.463us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 30.330s 1004.463us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 30.330s 1004.463us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 30.330s 1004.463us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 32.530s 3769.721us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1582.070s 184730.127us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 32.530s 3769.721us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 666.970s 55002.847us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 666.970s 55002.847us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 7.520s 248.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 35.200s 2438.770us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 68908531732107348659302045435514029867343617464468706425649583965683264053369 172
UVM_INFO @ 403576894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 1674314122000466256558682706706461860438625006721260518718840315248455998006 104
UVM_INFO @ 2438770310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---