Simulation Results: chip

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.78 %
  • code
  • 84.19 %
  • assert
  • 97.37 %
  • func
  • 39.79 %
  • line
  • 94.23 %
  • branch
  • 93.76 %
  • cond
  • 89.29 %
  • toggle
  • 86.55 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
75.45%
V2S
100.00%
V3
65.38%
unmapped
54.55%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 175.160s 3002.080us 1 1 100.00
chip_sw_example_rom 75.270s 2236.552us 1 1 100.00
chip_sw_example_manufacturer 175.400s 3808.364us 1 1 100.00
chip_sw_example_concurrency 158.270s 2799.153us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 156.540s 4793.711us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 477.920s 6101.515us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 472.900s 6372.601us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4426.800s 30053.729us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 81.310s 2504.307us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4426.800s 30053.729us 1 1 100.00
chip_csr_rw 477.920s 6101.515us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.660s 44.720us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 310.100s 5576.626us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 310.100s 5576.626us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 310.100s 5576.626us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 382.790s 4617.563us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 382.790s 4617.563us 1 1 100.00
chip_sw_uart_tx_rx_idx1 385.590s 5324.214us 1 1 100.00
chip_sw_uart_tx_rx_idx2 372.150s 4757.770us 1 1 100.00
chip_sw_uart_tx_rx_idx3 359.920s 4892.764us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 332.620s 4548.590us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1871.110s 14056.130us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 304.700s 5564.257us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 241.230s 5905.628us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 241.230s 5905.628us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 206.010s 3727.432us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 330.100s 7123.301us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 246.990s 5921.575us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 97.920s 2278.637us 1 1 100.00
chip_tap_straps_testunlock0 95.470s 2816.579us 1 1 100.00
chip_tap_straps_rma 299.330s 5884.313us 1 1 100.00
chip_tap_straps_prod 125.180s 2939.258us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 555.620s 8185.445us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 555.620s 8185.445us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 565.970s 9611.811us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1894.300s 15821.849us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 381.860s 4911.127us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.960s 5476.698us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4137.140s 19974.951us 1 1 100.00
chip_sw_aes_enc_jitter_en 205.360s 2837.463us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 743.900s 7472.826us 1 1 100.00
chip_sw_hmac_enc_jitter_en 162.590s 3086.358us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 715.170s 7600.497us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 174.440s 4109.373us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 419.150s 5393.877us 1 1 100.00
chip_sw_clkmgr_jitter 145.670s 3026.297us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 254.860s 4225.754us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 442.040s 8255.032us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 284.360s 6174.580us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 143.260s 3430.287us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 284.360s 6174.580us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 197.670s 4107.743us 1 1 100.00
chip_sw_aes_smoketest 176.770s 3670.934us 1 1 100.00
chip_sw_aon_timer_smoketest 202.440s 3685.663us 1 1 100.00
chip_sw_clkmgr_smoketest 139.660s 3066.364us 1 1 100.00
chip_sw_csrng_smoketest 191.820s 3585.987us 1 1 100.00
chip_sw_entropy_src_smoketest 969.790s 7704.504us 1 1 100.00
chip_sw_gpio_smoketest 191.540s 4332.465us 1 1 100.00
chip_sw_hmac_smoketest 215.360s 3450.657us 1 1 100.00
chip_sw_kmac_smoketest 219.260s 3389.448us 1 1 100.00
chip_sw_otbn_smoketest 1196.670s 9604.024us 1 1 100.00
chip_sw_pwrmgr_smoketest 353.600s 7675.079us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 384.890s 8936.382us 1 1 100.00
chip_sw_rv_plic_smoketest 208.590s 3666.365us 1 1 100.00
chip_sw_rv_timer_smoketest 212.480s 4104.854us 1 1 100.00
chip_sw_rstmgr_smoketest 144.160s 2478.732us 1 1 100.00
chip_sw_sram_ctrl_smoketest 189.770s 3809.138us 1 1 100.00
chip_sw_uart_smoketest 177.470s 2762.197us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 190.670s 3961.524us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 388.650s 5723.208us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8107.270s 61116.210us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3328.630s 17914.249us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 11.587s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1056.980s 15686.406us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 916.580s 15402.410us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7297.460s 55894.867us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7120.360s 56425.974us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 64.960s 2712.578us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 64.960s 2712.578us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4426.800s 30053.729us 1 1 100.00
chip_same_csr_outstanding 1587.710s 14671.195us 1 1 100.00
chip_csr_hw_reset 156.540s 4793.711us 1 1 100.00
chip_csr_rw 477.920s 6101.515us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4426.800s 30053.729us 1 1 100.00
chip_same_csr_outstanding 1587.710s 14671.195us 1 1 100.00
chip_csr_hw_reset 156.540s 4793.711us 1 1 100.00
chip_csr_rw 477.920s 6101.515us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 25.650s 1081.121us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.550s 45.703us 1 1 100.00
xbar_smoke_large_delays 45.670s 7603.538us 1 1 100.00
xbar_smoke_slow_rsp 56.970s 4687.231us 1 1 100.00
xbar_random_zero_delays 32.240s 537.747us 1 1 100.00
xbar_random_large_delays 222.770s 35010.696us 1 1 100.00
xbar_random_slow_rsp 127.260s 14026.745us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 5.680s 88.966us 1 1 100.00
xbar_error_and_unmapped_addr 27.840s 890.237us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 24.320s 441.846us 1 1 100.00
xbar_error_and_unmapped_addr 27.840s 890.237us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 70.910s 3148.401us 1 1 100.00
xbar_access_same_device_slow_rsp 69.430s 8950.874us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 11.280s 483.315us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 376.820s 16214.332us 1 1 100.00
xbar_stress_all_with_error 121.960s 2591.868us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 97.980s 214.819us 1 1 100.00
xbar_stress_all_with_reset_error 24.280s 150.867us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3328.630s 17914.249us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 441.310s 6943.769us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 460.150s 5811.691us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 41.724s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 8.536s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 15.434s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 40.527s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 8.984s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 33.402s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 10.642s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 19.154s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21.085s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 39.503s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 113.566s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 42.051s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 23.535s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 46.527s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 101.329s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 20.980s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 25.710s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 23.190s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 20.390s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 20.730s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 21.840s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 25.040s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 22.880s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 19.910s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.250s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 19.640s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.790s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 21.450s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19.810s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 19.440s 10.400us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 117.249s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 69.246s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 64.150s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 62.029s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 34.742s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 6190.940s 29659.624us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 6163.340s 34697.092us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6005.540s 29958.938us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3224.850s 16288.062us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3213.270s 35037.874us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3213.270s 35037.874us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 163.630s 3118.527us 1 1 100.00
chip_sw_aes_enc_jitter_en 205.360s 2837.463us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 200.880s 3042.603us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 151.390s 3154.625us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 752.680s 9044.436us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 220.620s 3906.242us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 363.080s 6196.832us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 421.940s 5934.056us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 500.950s 4994.363us 1 1 100.00
chip_plic_all_irqs_10 315.470s 3750.726us 1 1 100.00
chip_plic_all_irqs_20 334.690s 4409.840us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 211.120s 3211.761us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 936.310s 12186.421us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 293.150s 4540.107us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 191.890s 3832.234us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.215s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 911.720s 8562.780us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1125.500s 8498.609us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 851.210s 8038.533us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9419.380s 255920.345us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 251.860s 5186.060us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 353.600s 7675.079us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 251.860s 5186.060us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 407.470s 7414.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 407.470s 7414.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 314.710s 7480.587us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 387.760s 6560.820us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 573.230s 6258.222us 1 1 100.00
chip_sw_aes_idle 151.390s 3154.625us 1 1 100.00
chip_sw_hmac_enc_idle 176.620s 3149.128us 1 1 100.00
chip_sw_kmac_idle 158.390s 3467.250us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 283.830s 4612.961us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 260.320s 3820.381us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 391.570s 5771.218us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 412.700s 5973.994us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 754.870s 15698.829us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 408.460s 5124.751us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 411.480s 5527.363us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 400.640s 4630.495us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 438.350s 5877.098us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 421.080s 4460.266us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 398.090s 5665.604us 1 1 100.00
chip_sw_ast_clk_outputs 565.970s 9611.811us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 367.270s 9569.496us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 400.640s 4630.495us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 438.350s 5877.098us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 381.860s 4911.127us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.960s 5476.698us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4137.140s 19974.951us 1 1 100.00
chip_sw_aes_enc_jitter_en 205.360s 2837.463us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 743.900s 7472.826us 1 1 100.00
chip_sw_hmac_enc_jitter_en 162.590s 3086.358us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 715.170s 7600.497us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 174.440s 4109.373us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 419.150s 5393.877us 1 1 100.00
chip_sw_clkmgr_jitter 145.670s 3026.297us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 195.440s 3570.443us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 462.200s 6021.537us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 615.460s 7133.091us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4205.280s 25407.539us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 191.900s 3226.638us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 193.990s 3794.092us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 617.670s 8384.209us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 195.810s 4426.300us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 410.170s 5841.789us 1 1 100.00
chip_sw_flash_init_reduced_freq 1487.650s 31638.673us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 17916.500s 199035.111us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 565.970s 9611.811us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 384.500s 5025.177us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 266.970s 3830.398us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 421.940s 5934.056us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 911.720s 8562.780us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2017.760s 25605.102us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 273.840s 4727.124us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 537.430s 9119.488us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 181.080s 3402.747us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 5774.750s 30964.451us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 137.450s 3248.938us 1 1 100.00
chip_sw_edn_entropy_reqs 993.620s 8985.600us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 137.450s 3248.938us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2017.760s 25605.102us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 178.070s 3359.287us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1403.410s 31340.833us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 622.670s 6161.790us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.960s 5476.698us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 412.490s 4173.729us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 381.860s 4911.127us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3898.720s 45929.531us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1403.410s 31340.833us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 269.560s 3387.894us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1201.360s 10292.250us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.160s 3380.184us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3898.720s 45929.531us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.160s 3380.184us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.160s 3380.184us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.160s 3380.184us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.160s 3380.184us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 421.940s 5934.056us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 476.630s 15387.224us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 618.290s 6129.791us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 459.530s 7180.961us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 459.530s 7180.961us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 201.420s 3611.574us 1 1 100.00
chip_sw_hmac_enc_jitter_en 162.590s 3086.358us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 176.620s 3149.128us 1 1 100.00
chip_sw_hmac_all_configurations 0 1 0.00
chip_sw_hmac_oneshot 1417.500s 12026.703us 0 1 0.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1507.730s 12026.733us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 508.900s 6473.516us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 381.230s 5715.107us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 383.580s 5429.730us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 312.070s 4098.607us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1201.360s 10292.250us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 715.170s 7600.497us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1334.590s 9993.458us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 752.680s 9044.436us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 3750.840s 20026.876us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 158.220s 3772.122us 1 1 100.00
chip_sw_kmac_mode_kmac 203.840s 3211.107us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 174.440s 4109.373us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1201.360s 10292.250us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 938.380s 14675.740us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 183.920s 3511.670us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 856.590s 6811.899us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 158.390s 3467.250us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 363.080s 6196.832us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 97.920s 2278.637us 1 1 100.00
chip_tap_straps_rma 299.330s 5884.313us 1 1 100.00
chip_tap_straps_prod 125.180s 2939.258us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 196.480s 4080.863us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 938.380s 14675.740us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 938.380s 14675.740us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 938.380s 14675.740us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 852.590s 9238.813us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 182.160s 3380.184us 0 1 0.00
chip_sw_flash_rma_unlocked 3898.720s 45929.531us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 219.010s 4437.803us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 520.560s 6869.681us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 559.630s 8687.218us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 425.560s 6050.123us 0 1 0.00
chip_sw_lc_ctrl_transition 938.380s 14675.740us 1 1 100.00
chip_sw_keymgr_key_derivation 1201.360s 10292.250us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 374.290s 10643.575us 1 1 100.00
chip_sw_sram_ctrl_execution_main 703.870s 13066.246us 1 1 100.00
chip_prim_tl_access 476.630s 15387.224us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 367.270s 9569.496us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 408.460s 5124.751us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 411.480s 5527.363us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 400.640s 4630.495us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 438.350s 5877.098us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 421.080s 4460.266us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 398.090s 5665.604us 1 1 100.00
chip_tap_straps_dev 97.920s 2278.637us 1 1 100.00
chip_tap_straps_rma 299.330s 5884.313us 1 1 100.00
chip_tap_straps_prod 125.180s 2939.258us 1 1 100.00
chip_rv_dm_lc_disabled 191.340s 6131.371us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 155.310s 4142.724us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 108.770s 4042.117us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 99.960s 3938.626us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 224.280s 4141.892us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 2348.460s 44770.239us 1 1 100.00
chip_rv_dm_lc_disabled 191.340s 6131.371us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 765.860s 14513.327us 0 1 0.00
chip_sw_lc_walkthrough_prod 746.330s 11526.528us 0 1 0.00
chip_sw_lc_walkthrough_prodend 719.970s 14626.313us 1 1 100.00
chip_sw_lc_walkthrough_rma 392.850s 7419.931us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2348.460s 44770.239us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 1 3 33.33
chip_sw_lc_ctrl_volatile_raw_unlock 783.990s 27198.981us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 95.850s 3362.331us 1 1 100.00
rom_volatile_raw_unlock 77.691s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3877.890s 17502.108us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4137.140s 19974.951us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 573.230s 6258.222us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 573.230s 6258.222us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 573.230s 6258.222us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 336.680s 3664.197us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 938.380s 14675.740us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1403.410s 31340.833us 1 1 100.00
chip_sw_otbn_mem_scramble 336.680s 3664.197us 1 1 100.00
chip_sw_keymgr_key_derivation 1201.360s 10292.250us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 358.760s 5104.268us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 186.950s 4156.464us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1403.410s 31340.833us 1 1 100.00
chip_sw_otbn_mem_scramble 336.680s 3664.197us 1 1 100.00
chip_sw_keymgr_key_derivation 1201.360s 10292.250us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 358.760s 5104.268us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 186.950s 4156.464us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 938.380s 14675.740us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 427.410s 7381.144us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 196.480s 4080.863us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 219.010s 4437.803us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 520.560s 6869.681us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 559.630s 8687.218us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 425.560s 6050.123us 0 1 0.00
chip_sw_lc_ctrl_transition 938.380s 14675.740us 1 1 100.00
chip_prim_tl_access 476.630s 15387.224us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 476.630s 15387.224us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 841.260s 8573.786us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 194.810s 6330.597us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1263.150s 33606.309us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 268.530s 8458.904us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 434.130s 8324.252us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 521.120s 7678.577us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1000.840s 25966.851us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 253.260s 5779.480us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 407.470s 7414.000us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 861.080s 14542.348us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 427.500s 5595.074us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 194.810s 6330.597us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 356.050s 5291.899us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1272.630s 21313.290us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 290.690s 6725.933us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 186.080s 3568.715us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 229.990s 6160.342us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 628.850s 9170.917us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 925.020s 15486.849us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1984.660s 30385.660us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 219.270s 3402.180us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 421.940s 5934.056us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 374.290s 10643.575us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 374.290s 10643.575us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 925.020s 15486.849us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 229.990s 6160.342us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 427.500s 5595.074us 1 1 100.00
chip_sw_pwrmgr_smoketest 353.600s 7675.079us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 256.390s 6131.196us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 408.870s 7051.939us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 332.110s 6451.168us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 936.310s 12186.421us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 164.640s 3793.350us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 421.940s 5934.056us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1125.500s 8498.609us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 557.280s 6168.427us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 532.130s 5885.724us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 200.930s 4143.517us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 186.950s 4156.464us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 408.870s 7051.939us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 408.870s 7051.939us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 130.460s 3292.397us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 617.510s 9882.551us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1059.110s 14100.192us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 256.390s 6131.196us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 236.850s 4247.748us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1426.040s 12868.866us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 299.330s 5884.313us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 191.340s 6131.371us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 500.950s 4994.363us 1 1 100.00
chip_plic_all_irqs_10 315.470s 3750.726us 1 1 100.00
chip_plic_all_irqs_20 334.690s 4409.840us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 231.340s 3134.127us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 218.670s 4269.949us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3328.630s 17914.249us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 340.320s 5401.244us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 245.550s 3409.502us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 254.350s 3437.473us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 174.070s 2973.756us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 358.760s 5104.268us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 419.150s 5393.877us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 515.690s 9199.310us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 492.610s 9392.504us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 703.870s 13066.246us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 421.940s 5934.056us 1 1 100.00
chip_sw_data_integrity_escalation 555.620s 8185.445us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 628.850s 9170.917us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1071.680s 24246.332us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 151.720s 2618.908us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 255.050s 3741.291us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 378.870s 5335.591us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1071.680s 24246.332us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1071.680s 24246.332us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2341.920s 20183.282us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2341.920s 20183.282us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 375.450s 7953.619us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3213.270s 35037.874us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 209.290s 4416.803us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 166.710s 3033.025us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 255.220s 4075.375us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 363.190s 4654.879us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1021.190s 9023.057us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4994.260s 31815.972us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1950.160s 12284.990us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 198.060s 3744.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 206.460s 3896.364us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 141.040s 3159.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9707.300s 69094.816us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1097.660s 7420.901us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 215.650s 5221.398us 0 1 0.00
rom_e2e_jtag_debug_dev 187.910s 3875.205us 0 1 0.00
rom_e2e_jtag_debug_rma 257.810s 4909.287us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 106.700s 3810.214us 0 1 0.00
rom_e2e_jtag_inject_dev 87.330s 3182.044us 0 1 0.00
rom_e2e_jtag_inject_rma 97.930s 2829.618us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 28.157s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 260.400s 3414.458us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 339.480s 3465.680us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1027.790s 6761.257us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1527.630s 11201.125us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 249.690s 2387.510us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 608.510s 6179.046us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 92.430s 2511.229us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 259.320s 3822.720us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 339.090s 7853.445us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 422.260s 6404.095us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 925.020s 15486.849us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 215.650s 5221.398us 0 1 0.00
rom_e2e_jtag_debug_dev 187.910s 3875.205us 0 1 0.00
rom_e2e_jtag_debug_rma 257.810s 4909.287us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 377.620s 6517.789us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 421.940s 5934.056us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5519.890s 38662.909us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5519.890s 38662.909us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 172.590s 3502.789us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 382.790s 4617.563us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3284.780s 19474.463us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 11 54.55
chip_sival_flash_info_access 240.590s 3214.155us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 20.040s 10.340us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 7.050s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 146.280s 3318.133us 1 1 100.00
chip_sw_otp_ctrl_descrambling 219.550s 3052.967us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 171.940s 3643.302us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.759s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 192.820s 3289.404us 1 1 100.00
ate_bootstrap_flash_erase 529.330s 10010.380us 0 1 0.00
ate_bootstrap_one_frame 6363.820s 43514.869us 1 1 100.00
ate_bootstrap_disjoint 9587.970s 79008.815us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 58115228984137393652528390805722525396000051281656826686662263689758360957202 None
---- STDERR ----
Another command (pid=2080019) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 93378569674376068361732736925078078860017141972976615616706516461287554333461 None
Another command (pid=450167) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=431298) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=462948) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 58626183286019416256445992346612837826370978263206150909582975381300173550375 None
---- STDERR ----
Another command (pid=566650) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=562388) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 1526203536504986033144524131419462096344373077566050932806481632631224124295 None
Another command (pid=590708) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=589546) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=604752) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 80005062746278729042593518527560299483619626235624379351822542315428242786296 None
Another command (pid=626890) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=653158) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=625896) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 97527714732126599457564079763113409366691198473163485892732712780431628136633 None
---- STDERR ----
Another command (pid=569855) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 13646508122661765467140852445781940517608482624450474435089703779553340180787 None
---- STDERR ----
Another command (pid=376975) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 91582218209260705341971730084870078332411072612485933163166550908380013014265 None
Another command (pid=568798) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=566650) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=562388) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 73059693431731223400945193935016146722868161380768661380587878240939815635740 None
Another command (pid=582254) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=569855) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=598151) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 71846219196281150637179266777146603681733264327913461371862676907076969431240 None
Another command (pid=577610) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=589546) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=604752) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 33641609268129609986952722843037399118506747157075822427387089561846003137711 None
Another command (pid=381487) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=624495) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=583282) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 29325344208662965918464515562840609888506373907961881785193222095754734820693 None
Another command (pid=464309) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=472002) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=387018) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 33013490793095080869462061151522334347945241087025423164545894460826233098224 None
Another command (pid=569855) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=599746) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=590708) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 96164795453129865678652768196579048881144031270429698644781973572974974838335 None
Another command (pid=566650) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=562388) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=576233) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 14684461710681063150233691147015427613845734085284446552567680232908757730569 None
Another command (pid=644275) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=646759) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=569289) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 22394513245890559570602480467104574014243781233395202024796034117430884344293 None
Another command (pid=786330) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=757761) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=750765) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 44313638361409289034833983579278791831001949206109772474623768569533845238171 None
Another command (pid=411471) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=465928) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=559648) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 55478516435548241885577256509845234270449164134403219996271834596827902303355 None
Another command (pid=461685) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=481500) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=411471) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 44311091756417266135843106146900528987321326354729255441199850737040993294178 None
---- STDERR ----
Another command (pid=452559) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=461685) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 76598485311572455925793531766736823926913396383382721820684847248729010707691 None
---- STDERR ----
Another command (pid=452559) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 61860275390098891694441752813685912507984118537945377430060277667340223596919 None
---- STDERR ----
Another command (pid=452559) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=461685) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 65801696371789771613667605523895658956840840391644896702195546209937576854808 None
Another command (pid=462142) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=558994) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=464309) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 104126861495807811264379903276825054657525379497549046301475153371049064241030 None
---- STDERR ----
Another command (pid=376975) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 27333965522650452714375884993073678127559608189035982444801795350863617492817 None
Another command (pid=376975) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=444100) is running. Waiting for it to complete on the server (server_pid=264987)...
Another command (pid=450167) is running. Waiting for it to complete on the server (server_pid=264987)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 53929660533432866009994079963509339004395983989547820487588040621111556372390 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 20217315550743585245238217207226733306674622331761041980062335850220497113677 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 61651824880951497759843993865180509489026829928881527541499140448396380016200 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 3530367790846177429339339320013250116487752903223873091483023849838211584585 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 44823180554789800000613066776049303577214227807951671690376111373212762910528 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 86044831596382691491535326959987965940215206545682100613395391476312426438374 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 56280538109795374295830786725109021710333098326709519921311290261443717207829 368
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 35061151344220029076248703179982835469288495332972561128245915696744842887102 367
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 47958481571196077339092015352086429083492700098664105782343440334614143749176 366
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 22866450987171443982622513361974608069653483200816173112144891676149881992075 325
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 98773282803432194994484922122851569099278040588596930702195010085868116422037 328
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 39728189682720778951751506664898111064680496084391836334315238836860405946330 327
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 9397133516264362581314819785311052412439283529422953875171285584764052691183 315
UVM_ERROR @ 6160.342500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6160.342500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 90382535084846351768693938794778774268260095097241677969382196423858392141844 314
UVM_ERROR @ 5779.480000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5779.480000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 107454003069357179646659665022497742855988679032227191471429223145410448526585 325
UVM_ERROR @ 8324.252000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8324.252000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 28701378877527132700638199822902273714169717048495731984266205948581445628104 367
UVM_ERROR @ 21313.290000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 21313.290000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 18130455212136071771104511286010162193556467326347800470950659185583728471217 319
UVM_ERROR @ 7414.000000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7414.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 27364571609743496722559250717124325371796262275149589879643124642703743963296 369
UVM_INFO @ 14513.326670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 26710165694286583779660797896672688876978682966828330799056666340639975858413 369
UVM_INFO @ 11526.528036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 108002567890953160133071761600190669137007293726405096609754695752871878210519 341
UVM_INFO @ 7419.931280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 3 test runs
chip_sw_hmac_oneshot 104547630955254680460371312841141202887965838069659397608702697062498632192866 310
UVM_INFO @ 12026.702979 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 26157947287945222484152425001217739199572922336602142170537378137125906499888 347
UVM_INFO @ 12026.732616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 43595702712158397077619467618686521174072125454169229624283657119937898809370 334
UVM_INFO @ 20026.876262 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 46205922862291039000708140538656975219613613990766320961450008480089986383781 327
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 93973968780516154699876871421494867783038680901825245672582694685637187217759 327
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 82853944601012074256739265495470232938567819397706670382236147616602768106652 325
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 7349833275347319654672621533851814268735924037818711513992006548474333690035 217
TL item was: req: (cip_tl_seq_item@34458) { a_addr: 'h10380 a_data: 'h67a09c5c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1ba42 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2712.578120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 72354659457852291425201503638642359043944647394259808002093323050968526598667 224
TL item was: req: (cip_tl_seq_item@30514) { a_addr: 'h106f4 a_data: 'h7a75c8c2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h4 a_user: 'h1b67f d_param: 'h0 d_source: 'h3b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2504.307438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 100214527079814316802441589904264468007600226131335639764889236180339175773568 363
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 75694666294960860992998771645739710487210372923888938567333758270563343204905 325
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 114206098632368611076551657529689333722293597973169137146712553070034915062020 368
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 74855472785302246152086259704132474243154041266688777010319248005706957943391 327
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 36673023366810982736567196757451202002650498622902964891261911334782018539728 301
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 85537660036795631127574893126782118990902501616718968827879420087637469904068 327
UVM_INFO @ 3409.501840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 82069618036564604533198445862088932074444511916203246438545912848574683694827 309
UVM_INFO @ 3380.184250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 14881513215545386854287782241795266417985833625518183724078930703036842758987 342
UVM_INFO @ 6050.122585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 70634758936912138854710374433814805588597516989752195555387894929885516247666 316
UVM_ERROR @ 3822.720024 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3822.720024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 107014690839427421498772320133136261889067392818211546991471496827520018406003 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock 26455617547821763606391941536728108997276953735797320299498814017239555866787 308
UVM_INFO @ 27198.981413 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 42659848036849516320721957610656566547175601350625799679298694832693989207001 322
UVM_ERROR @ 6330.597366 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6330.597366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 35004435219231022028372164665981134934703776450703059427023473470772498942875 313
UVM_ERROR @ 3568.714728 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3568.714728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 49423531880023370416093196254658706326951643535295570971339002015494401743000 332
UVM_INFO @ 35037.874187 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:387)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 97371785600596103634207894198833232672401974114078741376574676290638791104832 307
UVM_INFO @ 3906.242253 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 64126413679443405295879443604055789889592386060628790073335660874851937659626 308
UVM_INFO @ 3832.234100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 90543917460299645467234949135111046789977238501981499377219418643020825596588 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 33962136141484183361189117310011044946518137052888137533071618432446693623984 343
UVM_INFO @ 3414.458223 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() 1 test run
chip_sw_pwrmgr_lowpower_cancel 36792025050939927500140537106480892750275357015450684238793135209980569818468 311
UVM_INFO @ 3643.301920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 97556360726622540561095753640605175079532772413628246372874975530787696625008 329
UVM_INFO @ 12868.866344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 17768017984782913231440092530800848279313631558116487292881422768152994040111 236
UVM_INFO @ 6131.370773 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 40802291181127313057725638147387106081582672239900159930673087699868565711798 318
UVM_INFO @ 15686.405544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 69621179601080040514113919498270827757981357875089171984050735831769690199577 329
UVM_INFO @ 15402.410173 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 93959781968747059325596680366108402775573044398630980718843221195956851234580 327
UVM_INFO @ 15821.849143 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 99377463270950919583064738535619044516690364852881630522521071622798596255825 272
UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 47943476196043360996838651970270799742783642189824198751802379815195780249231 319
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 5811.691199 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 92287634365155474328121744647462507791778578912443037003898688730833648176217 312
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 6943.769165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 43379999880303773970418502246734425819629523406751681409811753474912264271477 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 87365382957451174253277704760538717029498632002256544180496674925290529597836 327
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_rma 60416985508967099527030179556138738791291834552048032291226407191300807747172 318
UVM_INFO @ 4909.286796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 12672213582080812341500273741905888014318764060253122047329159608249891087669 327
UVM_ERROR @ 5723.208052 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5723.208052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---