Simulation Results: clkmgr

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.15 %
  • code
  • 98.20 %
  • assert
  • 95.48 %
  • func
  • 85.76 %
  • line
  • 98.97 %
  • branch
  • 98.59 %
  • cond
  • 94.27 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.820s 26.755us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 18.320us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.730s 15.790us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.100s 498.232us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.440s 153.358us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.620s 40.112us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.730s 15.790us 1 1 100.00
clkmgr_csr_aliasing 1.440s 153.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.680s 17.451us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.020s 88.257us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.750s 17.549us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.790s 107.206us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.820s 26.755us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.820s 797.383us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 10.620s 2422.646us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.820s 797.383us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 18.590s 7752.858us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.730s 14.537us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.150s 48.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.150s 48.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 18.320us 1 1 100.00
clkmgr_csr_rw 0.730s 15.790us 1 1 100.00
clkmgr_csr_aliasing 1.440s 153.358us 1 1 100.00
clkmgr_same_csr_outstanding 1.040s 127.080us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 18.320us 1 1 100.00
clkmgr_csr_rw 0.730s 15.790us 1 1 100.00
clkmgr_csr_aliasing 1.440s 153.358us 1 1 100.00
clkmgr_same_csr_outstanding 1.040s 127.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.790s 16.859us 0 1 0.00
clkmgr_tl_intg_err 21.620s 10086.288us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.730s 197.178us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.730s 197.178us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.730s 197.178us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.730s 197.178us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.130s 355.330us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 21.620s 10086.288us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.820s 797.383us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 10.620s 2422.646us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.730s 197.178us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.070s 137.351us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.800s 217.439us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.760s 28.729us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.920s 80.490us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.750s 24.607us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.730s 15.790us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.790s 16.859us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.730s 15.790us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.730s 15.790us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.790s 16.859us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.600s 820.521us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 38.660s 4550.313us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 57049437396224361000030778997869740562017290252877704447856942489477943413253 85
UVM_INFO @ 16859098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 93941253137254732122848333462034109703263366226877405668973630475281090833381 120
UVM_INFO @ 10086288337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---