Simulation Results: csrng

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.00 %
  • code
  • 92.33 %
  • assert
  • 93.23 %
  • func
  • 78.43 %
  • block
  • 96.95 %
  • line
  • 97.73 %
  • branch
  • 92.51 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 77.781us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 24.818us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 22.645us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 11.000s 344.114us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 166.093us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 23.296us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 22.645us 1 1 100.00
csrng_csr_aliasing 3.000s 166.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 420.745us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 205.505us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 205.505us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 579.000s 39548.979us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 32.336us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 48.824us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 78.088us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 78.088us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 24.818us 1 1 100.00
csrng_csr_rw 1.000s 22.645us 1 1 100.00
csrng_csr_aliasing 3.000s 166.093us 1 1 100.00
csrng_same_csr_outstanding 2.000s 24.765us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 24.818us 1 1 100.00
csrng_csr_rw 1.000s 22.645us 1 1 100.00
csrng_csr_aliasing 3.000s 166.093us 1 1 100.00
csrng_same_csr_outstanding 2.000s 24.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 93.477us 1 1 100.00
csrng_tl_intg_err 6.000s 439.253us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 3.437us 0 1 0.00
csrng_csr_rw 1.000s 22.645us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 420.745us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 579.000s 39548.979us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
csrng_sec_cm 4.000s 93.477us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
csrng_sec_cm 4.000s 93.477us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
csrng_sec_cm 4.000s 93.477us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
csrng_sec_cm 4.000s 93.477us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
csrng_sec_cm 4.000s 93.477us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 420.745us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 579.000s 39548.979us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 420.745us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 439.253us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
csrng_sec_cm 4.000s 93.477us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
csrng_sec_cm 4.000s 93.477us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 63.225us 1 1 100.00
csrng_err 2.000s 28.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 435431028178144530908644453758334996244236215829092200976518147198938648472 100
UVM_INFO @ 205505054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 60588196749190194057677248724636575890510723179473095932157535889173110317191 99
UVM_INFO @ 3437179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 74942693965818773642825496797403080975491317056535102033364897277541117110839 None