Simulation Results: edn/edn0

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.08 %
  • code
  • 79.73 %
  • assert
  • 96.53 %
  • func
  • 78.97 %
  • line
  • 97.23 %
  • branch
  • 90.52 %
  • cond
  • 84.62 %
  • toggle
  • 77.34 %
  • FSM
  • 48.92 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 47.654us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.890s 19.411us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 40.326us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.850s 314.227us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.140s 29.516us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.220s 30.695us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 40.326us 1 1 100.00
edn_csr_aliasing 1.140s 29.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 264.517us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 264.517us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 264.517us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 81.534us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.070s 55.238us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 21.312us 1 1 100.00
disable 1 2 50.00
edn_disable 0.780s 30.521us 1 1 100.00
edn_disable_auto_req_mode 1.770s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 5.220s 446.214us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.820s 25.763us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 55.013us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.100s 73.743us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.100s 73.743us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.890s 19.411us 1 1 100.00
edn_csr_rw 0.740s 40.326us 1 1 100.00
edn_csr_aliasing 1.140s 29.516us 1 1 100.00
edn_same_csr_outstanding 1.100s 34.427us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.890s 19.411us 1 1 100.00
edn_csr_rw 0.740s 40.326us 1 1 100.00
edn_csr_aliasing 1.140s 29.516us 1 1 100.00
edn_same_csr_outstanding 1.100s 34.427us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.250s 561.261us 1 1 100.00
edn_tl_intg_err 1.540s 420.031us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.900s 81.523us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.070s 55.238us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.250s 561.261us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.250s 561.261us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.250s 561.261us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.250s 561.261us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.070s 55.238us 1 1 100.00
edn_sec_cm 3.250s 561.261us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.070s 55.238us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.540s 420.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 66.060s 3770.316us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 89726346210056358040939743423918261642150151007467847961509865381340675585180 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---