Simulation Results: edn/edn1

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.61 %
  • code
  • 83.28 %
  • assert
  • 97.14 %
  • func
  • 79.41 %
  • line
  • 98.25 %
  • branch
  • 93.94 %
  • cond
  • 91.00 %
  • toggle
  • 87.74 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 19.359us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 34.736us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 19.810us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.670s 50.188us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.950s 151.214us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.990s 19.824us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 19.810us 1 1 100.00
edn_csr_aliasing 0.950s 151.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 69.086us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 69.086us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 69.086us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.710s 41.172us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.060s 32.107us 1 1 100.00
errs 1 1 100.00
edn_err 0.840s 20.719us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 15.062us 1 1 100.00
edn_disable_auto_req_mode 0.890s 120.078us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.580s 437.370us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.680s 21.087us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 17.470us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.400s 27.548us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.400s 27.548us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 34.736us 1 1 100.00
edn_csr_rw 0.850s 19.810us 1 1 100.00
edn_csr_aliasing 0.950s 151.214us 1 1 100.00
edn_same_csr_outstanding 1.180s 39.889us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 34.736us 1 1 100.00
edn_csr_rw 0.850s 19.810us 1 1 100.00
edn_csr_aliasing 0.950s 151.214us 1 1 100.00
edn_same_csr_outstanding 1.180s 39.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.410s 689.061us 1 1 100.00
edn_tl_intg_err 2.130s 107.826us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 17.874us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.060s 32.107us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.410s 689.061us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.410s 689.061us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.410s 689.061us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.410s 689.061us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.060s 32.107us 1 1 100.00
edn_sec_cm 2.410s 689.061us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.060s 32.107us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.130s 107.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.510s 2891.973us 1 1 100.00