Simulation Results: entropy_src/rng_4bits

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.62 %
  • code
  • 88.03 %
  • assert
  • 84.56 %
  • func
  • 57.28 %
  • block
  • 94.25 %
  • line
  • 96.94 %
  • branch
  • 86.36 %
  • toggle
  • 76.10 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 1.000s 34.032us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 106.809us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 27.134us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 120.068us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 238.631us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 22.189us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 27.134us 1 1 100.00
entropy_src_csr_aliasing 3.000s 238.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 1.000s 34.032us 1 1 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
entropy_src_fw_ov 221.000s 13067.509us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 221.000s 13067.509us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 409.000s 14019.318us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
entropy_src_intr 9.000s 5698.756us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
entropy_src_functional_alerts 5.000s 2108.479us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 198.000s 13153.992us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 119.172us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 31.497us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 22.738us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 21.931us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 118.497us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 118.497us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 106.809us 1 1 100.00
entropy_src_csr_rw 2.000s 27.134us 1 1 100.00
entropy_src_csr_aliasing 3.000s 238.631us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 76.409us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 106.809us 1 1 100.00
entropy_src_csr_rw 2.000s 27.134us 1 1 100.00
entropy_src_csr_aliasing 3.000s 238.631us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 76.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 173.808us 1 1 100.00
entropy_src_tl_intg_err 2.000s 69.607us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
entropy_src_cfg_regwen 1.000s 22.314us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
entropy_src_fw_ov 221.000s 13067.509us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 119.172us 1 1 100.00
entropy_src_sec_cm 2.000s 173.808us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 119.172us 1 1 100.00
entropy_src_sec_cm 2.000s 173.808us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 48.000s 14260.785us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 119.172us 1 1 100.00
entropy_src_sec_cm 2.000s 173.808us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 119.172us 1 1 100.00
entropy_src_sec_cm 2.000s 173.808us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 119.172us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 2108.479us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 69.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 201.000s 14076.549us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 10.000s 488.548us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 65941131949085413059462151944952177390714475218100364952456544341315636473280 470
UVM_INFO @ 488548269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 5270867332446209932002915060598812638264885438892527681961119784755687864005 113
UVM_INFO @ 22189069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---