Simulation Results: flash_ctrl

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 93.88 %
  • assert
  • 96.94 %
  • func
  • 95.82 %
  • line
  • 95.95 %
  • branch
  • 97.14 %
  • cond
  • 93.24 %
  • toggle
  • 96.02 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 38.780s 111.446us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.750s 32.620us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.330s 49.501us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.210s 117.728us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 32.600s 4078.394us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 23.720s 1632.038us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.620s 181.333us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.210s 117.728us 1 1 100.00
flash_ctrl_csr_aliasing 23.720s 1632.038us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 9.790s 17.831us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.150s 147.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.010s 23.631us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 26.200s 105.348us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1239.940s 343542.791us 1 1 100.00
flash_ctrl_hw_rma_reset 600.390s 100160.931us 1 1 100.00
flash_ctrl_lcmgr_intg 8.810s 23.759us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1216.660s 1692319.526us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 175.220s 4115.745us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.130s 35.375us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1707.610s 455269.947us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 49.810s 740.880us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.520s 81.334us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.740s 33.102us 1 1 100.00
flash_ctrl_re_evict 17.190s 382.992us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 154.610s 736.813us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 154.610s 736.813us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 221.970s 21577.053us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 16.150s 710.401us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 136.210s 186.540us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 327.870s 4543.035us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 326.300s 743.223us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1305.830s 3438.191us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.740s 81.931us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 168.640s 40545.956us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.880s 21.037us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.520s 54.578us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 844.980s 1278.459us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 98.520s 2512.249us 1 1 100.00
flash_ctrl_otp_reset 48.750s 100.024us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1239.940s 343542.791us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 73.470s 610.938us 1 1 100.00
flash_ctrl_intr_wr 45.630s 4689.890us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 73.240s 11207.160us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 248.000s 255651.468us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 46.500s 4173.397us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 39.590s 2717.470us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 15.910s 31.256us 1 1 100.00
flash_ctrl_ro_derr 98.240s 754.823us 1 1 100.00
flash_ctrl_rw_derr 178.860s 14572.727us 1 1 100.00
flash_ctrl_derr_detect 98.190s 1959.820us 1 1 100.00
flash_ctrl_integrity 313.070s 4158.755us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.040s 39.737us 1 1 100.00
flash_ctrl_ro_serr 107.560s 4685.792us 1 1 100.00
flash_ctrl_rw_serr 136.610s 1880.405us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 32.930s 2716.483us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 41.470s 899.037us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 86.620s 4731.940us 1 1 100.00
flash_ctrl_write_word_sweep 7.090s 153.220us 1 1 100.00
flash_ctrl_read_word_sweep 6.520s 56.166us 1 1 100.00
flash_ctrl_ro 85.030s 741.641us 1 1 100.00
flash_ctrl_rw 337.060s 4172.962us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.930s 475.983us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 543.250s 80764.161us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 35.660s 10048.119us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.900s 21.357us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.520s 61.384us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.790s 122.987us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.790s 122.987us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.330s 49.501us 1 1 100.00
flash_ctrl_csr_rw 9.210s 117.728us 1 1 100.00
flash_ctrl_csr_aliasing 23.720s 1632.038us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.790s 245.945us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.330s 49.501us 1 1 100.00
flash_ctrl_csr_rw 9.210s 117.728us 1 1 100.00
flash_ctrl_csr_aliasing 23.720s 1632.038us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.790s 245.945us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 32.980s 100.859us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 32.980s 100.859us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 32.980s 100.859us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 32.980s 100.859us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 59.240s 314.319us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1836.530s 902.042us 1 1 100.00
flash_ctrl_tl_intg_err 159.790s 4612.807us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 159.790s 4612.807us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 159.790s 4612.807us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 19.000s 260.601us 1 1 100.00
flash_ctrl_wr_intg 7.030s 111.853us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 38.780s 111.446us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 48.750s 100.024us 1 1 100.00
flash_ctrl_disable 9.880s 21.037us 1 1 100.00
flash_ctrl_sec_info_access 40.850s 1706.455us 1 1 100.00
flash_ctrl_connect 7.520s 54.578us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.080s 32.773us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.210s 117.728us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.980s 100.859us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.210s 117.728us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.980s 100.859us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.210s 117.728us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.980s 100.859us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.880s 21.037us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 19.000s 260.601us 1 1 100.00
flash_ctrl_access_after_disable 10.240s 24.287us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.690s 28.719us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.880s 21.037us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 16.150s 710.401us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 337.060s 4172.962us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 136.610s 1880.405us 1 1 100.00
flash_ctrl_rw_derr 178.860s 14572.727us 1 1 100.00
flash_ctrl_integrity 313.070s 4158.755us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1239.940s 343542.791us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1836.530s 902.042us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1836.530s 902.042us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1836.530s 902.042us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1836.530s 902.042us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 12.130s 753.744us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 9.850s 23.968us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.390s 24.613us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1836.530s 902.042us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1836.530s 902.042us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1836.530s 902.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.540s 52.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 273.660s 2104.605us 1 1 100.00