Simulation Results: hmac

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.29 %
  • code
  • 97.00 %
  • assert
  • 97.60 %
  • func
  • 43.26 %
  • line
  • 99.69 %
  • branch
  • 98.68 %
  • cond
  • 95.45 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.950s 483.208us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.870s 109.474us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.940s 180.233us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.120s 914.074us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.150s 5417.799us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.240s 23.410us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.940s 180.233us 1 1 100.00
hmac_csr_aliasing 6.150s 5417.799us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 0.990s 24.196us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 10.690s 1388.511us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 206.210s 35983.014us 1 1 100.00
hmac_test_sha384_vectors 20.140s 2401.225us 1 1 100.00
hmac_test_sha512_vectors 20.490s 321.052us 1 1 100.00
hmac_test_hmac256_vectors 7.700s 387.251us 1 1 100.00
hmac_test_hmac384_vectors 10.990s 1722.096us 1 1 100.00
hmac_test_hmac512_vectors 12.250s 1108.529us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.070s 545.223us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 789.340s 36028.439us 1 1 100.00
error 1 1 100.00
hmac_error 56.660s 18188.936us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 42.430s 4819.664us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.950s 483.208us 1 1 100.00
hmac_long_msg 0.990s 24.196us 1 1 100.00
hmac_back_pressure 10.690s 1388.511us 1 1 100.00
hmac_datapath_stress 789.340s 36028.439us 1 1 100.00
hmac_burst_wr 3.070s 545.223us 1 1 100.00
hmac_stress_all 352.750s 6628.888us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.950s 483.208us 1 1 100.00
hmac_long_msg 0.990s 24.196us 1 1 100.00
hmac_back_pressure 10.690s 1388.511us 1 1 100.00
hmac_datapath_stress 789.340s 36028.439us 1 1 100.00
hmac_wipe_secret 42.430s 4819.664us 1 1 100.00
hmac_test_sha256_vectors 206.210s 35983.014us 1 1 100.00
hmac_test_sha384_vectors 20.140s 2401.225us 1 1 100.00
hmac_test_sha512_vectors 20.490s 321.052us 1 1 100.00
hmac_test_hmac256_vectors 7.700s 387.251us 1 1 100.00
hmac_test_hmac384_vectors 10.990s 1722.096us 1 1 100.00
hmac_test_hmac512_vectors 12.250s 1108.529us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.950s 483.208us 1 1 100.00
hmac_long_msg 0.990s 24.196us 1 1 100.00
hmac_back_pressure 10.690s 1388.511us 1 1 100.00
hmac_datapath_stress 789.340s 36028.439us 1 1 100.00
hmac_burst_wr 3.070s 545.223us 1 1 100.00
hmac_error 56.660s 18188.936us 1 1 100.00
hmac_wipe_secret 42.430s 4819.664us 1 1 100.00
hmac_test_sha256_vectors 206.210s 35983.014us 1 1 100.00
hmac_test_sha384_vectors 20.140s 2401.225us 1 1 100.00
hmac_test_sha512_vectors 20.490s 321.052us 1 1 100.00
hmac_test_hmac256_vectors 7.700s 387.251us 1 1 100.00
hmac_test_hmac384_vectors 10.990s 1722.096us 1 1 100.00
hmac_test_hmac512_vectors 12.250s 1108.529us 1 1 100.00
hmac_stress_all 352.750s 6628.888us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 352.750s 6628.888us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.680s 95.047us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.620s 285.494us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.890s 873.057us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.890s 873.057us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.870s 109.474us 1 1 100.00
hmac_csr_rw 0.940s 180.233us 1 1 100.00
hmac_csr_aliasing 6.150s 5417.799us 1 1 100.00
hmac_same_csr_outstanding 2.070s 417.322us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.870s 109.474us 1 1 100.00
hmac_csr_rw 0.940s 180.233us 1 1 100.00
hmac_csr_aliasing 6.150s 5417.799us 1 1 100.00
hmac_same_csr_outstanding 2.070s 417.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.840s 211.073us 1 1 100.00
hmac_tl_intg_err 2.040s 1586.904us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.040s 1586.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.950s 483.208us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.790s 143.693us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 70.040s 1709.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.160s 26.855us 1 1 100.00