Simulation Results: i2c

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.97 %
  • code
  • 78.95 %
  • assert
  • 97.25 %
  • func
  • 81.71 %
  • line
  • 96.75 %
  • branch
  • 92.69 %
  • cond
  • 85.42 %
  • toggle
  • 74.04 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
92.68%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 26.580s 1092.894us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 5.480s 5549.413us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.820s 22.564us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.840s 17.587us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.810s 169.459us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.800s 125.393us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.920s 115.773us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.840s 17.587us 1 1 100.00
i2c_csr_aliasing 1.800s 125.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.610s 501.918us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 0.860s 20.696us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 1537.710s 49734.822us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.710s 26.467us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 155.460s 4851.581us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 89.990s 8491.101us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.050s 105.262us 1 1 100.00
i2c_host_fifo_fmt_empty 14.390s 486.041us 1 1 100.00
i2c_host_fifo_reset_rx 1.820s 625.561us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 71.460s 7483.364us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 19.570s 8802.959us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.950s 588.509us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.020s 1315.821us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 21.640s 6105.328us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.970s 512.485us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 8.160s 1081.476us 1 1 100.00
i2c_target_intr_smoke 3.590s 4060.217us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.120s 258.359us 1 1 100.00
i2c_target_fifo_reset_tx 1.130s 270.357us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 9.510s 8054.537us 1 1 100.00
i2c_target_stress_rd 8.160s 1081.476us 1 1 100.00
i2c_target_intr_stress_wr 18.040s 12399.910us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.070s 2996.192us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 21.490s 4819.473us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.680s 1141.424us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.430s 602.598us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.330s 1997.771us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.140s 1110.946us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 1537.710s 49734.822us 1 1 100.00
i2c_host_perf_precise 5.710s 2488.913us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 19.570s 8802.959us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 5.710s 647.208us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.180s 1079.506us 1 1 100.00
i2c_target_nack_acqfull_addr 2.140s 454.395us 1 1 100.00
i2c_target_nack_txstretch 1.580s 1082.969us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 8.140s 581.588us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.230s 2319.375us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.890s 18.683us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.930s 22.694us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.620s 37.317us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.620s 37.317us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.820s 22.564us 1 1 100.00
i2c_csr_rw 0.840s 17.587us 1 1 100.00
i2c_csr_aliasing 1.800s 125.393us 1 1 100.00
i2c_same_csr_outstanding 1.140s 185.902us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.820s 22.564us 1 1 100.00
i2c_csr_rw 0.840s 17.587us 1 1 100.00
i2c_csr_aliasing 1.800s 125.393us 1 1 100.00
i2c_same_csr_outstanding 1.140s 185.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.640s 566.002us 1 1 100.00
i2c_sec_cm 0.990s 71.434us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.640s 566.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 27.540s 894.260us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.520s 252.349us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 0.820s 9.967us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 3 test runs
i2c_host_error_intr 93928277693111050313529417228504074633595431808607129181119070876386980079708 96
UVM_INFO @ 501917656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 65078176455975036025702357514436298081974783640603259668869768080450775971097 92
UVM_INFO @ 20695513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 6851222138715016580661537651964019376450996063894253851738099331138799809757 85
UVM_INFO @ 9966811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 101533155810235272830652642666176361870218354171078914075620597829816193834086 84
UVM_INFO @ 1315820900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 81164084958691519061112609280116039384872870748967106262815454828568697169824 78
UVM_INFO @ 252349030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 3183651198898489264677439856024445001424546649034592918804844305502415352298 105
UVM_INFO @ 894260464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---