Simulation Results: keymgr

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.51 %
  • code
  • 92.40 %
  • assert
  • 97.49 %
  • func
  • 51.65 %
  • line
  • 98.60 %
  • branch
  • 97.17 %
  • cond
  • 92.76 %
  • toggle
  • 87.40 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
94.74%
V2S
90.91%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.880s 206.313us 1 1 100.00
random 1 1 100.00
keymgr_random 11.170s 726.540us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.980s 197.699us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.500s 115.148us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 14.150s 8058.220us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 6.770s 2293.438us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.030s 54.940us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.500s 115.148us 1 1 100.00
keymgr_csr_aliasing 6.770s 2293.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 4.220s 390.817us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 1.510s 95.551us 1 1 100.00
keymgr_sideload_kmac 2.160s 182.347us 1 1 100.00
keymgr_sideload_aes 3.320s 318.897us 1 1 100.00
keymgr_sideload_otbn 1.640s 90.920us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 14.150s 747.249us 1 1 100.00
lc_disable 0 1 0.00
keymgr_lc_disable 5.900s 916.295us 0 1 0.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.320s 151.442us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 5.580s 1072.877us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.310s 338.427us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.950s 48.347us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 57.460s 9266.828us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.930s 50.118us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.930s 22.196us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.510s 54.393us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.510s 54.393us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.980s 197.699us 1 1 100.00
keymgr_csr_rw 1.500s 115.148us 1 1 100.00
keymgr_csr_aliasing 6.770s 2293.438us 1 1 100.00
keymgr_same_csr_outstanding 2.400s 139.716us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.980s 197.699us 1 1 100.00
keymgr_csr_rw 1.500s 115.148us 1 1 100.00
keymgr_csr_aliasing 6.770s 2293.438us 1 1 100.00
keymgr_same_csr_outstanding 2.400s 139.716us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
keymgr_tl_intg_err 2.020s 190.110us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.550s 337.374us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.550s 337.374us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.550s 337.374us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.550s 337.374us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.640s 1503.718us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 2.020s 190.110us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.550s 337.374us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 4.220s 390.817us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 11.170s 726.540us 1 1 100.00
keymgr_csr_rw 1.500s 115.148us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 11.170s 726.540us 1 1 100.00
keymgr_csr_rw 1.500s 115.148us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 11.170s 726.540us 1 1 100.00
keymgr_csr_rw 1.500s 115.148us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
keymgr_lc_disable 5.900s 916.295us 0 1 0.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.310s 338.427us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.310s 338.427us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 11.170s 726.540us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.660s 200.479us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 6.540s 1444.719us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 0 1 0.00
keymgr_lc_disable 5.900s 916.295us 0 1 0.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 6.540s 1444.719us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 6.540s 1444.719us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 6.540s 1444.719us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.730s 3315.760us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 6.540s 1444.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 7.480s 759.574us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Sealing Aes 1 test run
keymgr_lc_disable 81689939167005460317024651680446962060493291138239464808479211501629787263442 478
UVM_INFO @ 916294898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 68801637405903601216671463878385764207549776283502060351595025720293842421884 948
UVM_INFO @ 759574311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---