Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.62 %
  • code
  • 84.12 %
  • assert
  • 94.69 %
  • func
  • 93.06 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.01 %
  • toggle
  • 87.14 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.070s 64.689us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.010s 16.819us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 233.904us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.700s 468.302us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 140.843us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.250s 40.103us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 233.904us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 140.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.700s 109.021us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.020s 335.448us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.950s 161.967us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.270s 57.979us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.180s 1145.984us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_prog_failure 2.270s 57.979us 1 1 100.00
lc_ctrl_errors 6.180s 1145.984us 1 1 100.00
lc_ctrl_security_escalation 5.700s 4612.999us 1 1 100.00
lc_ctrl_jtag_state_failure 52.790s 12225.820us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.940s 597.025us 1 1 100.00
lc_ctrl_jtag_errors 24.400s 19162.577us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.060s 581.999us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.250s 952.139us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.940s 597.025us 1 1 100.00
lc_ctrl_jtag_errors 24.400s 19162.577us 1 1 100.00
lc_ctrl_jtag_access 5.870s 655.002us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.960s 1612.071us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.840s 167.396us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.910s 554.893us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.470s 540.771us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 11.930s 5266.118us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.290s 148.657us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.840s 670.790us 1 1 100.00
lc_ctrl_jtag_alert_test 1.230s 135.954us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.730s 553.794us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.880s 45.078us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 155.390s 7772.735us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.200s 45.517us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.050s 80.423us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.050s 80.423us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.010s 16.819us 1 1 100.00
lc_ctrl_csr_rw 0.850s 233.904us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 140.843us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.970s 109.279us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.010s 16.819us 1 1 100.00
lc_ctrl_csr_rw 0.850s 233.904us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 140.843us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.970s 109.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
lc_ctrl_tl_intg_err 1.580s 86.008us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.580s 86.008us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.020s 335.448us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.620s 1359.945us 1 1 100.00
lc_ctrl_sec_cm 9.580s 357.158us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.700s 4612.999us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.700s 109.021us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.250s 952.139us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.160s 965.857us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.160s 965.857us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.830s 367.690us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.070s 1309.704us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.070s 1309.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 77.420s 17849.232us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 56336740771048974956699233558627229963755428954679695371159438538606360098946 10768
UVM_INFO @ 17849232020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---