Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.88 %
  • code
  • 83.87 %
  • assert
  • 94.13 %
  • func
  • 91.64 %
  • line
  • 97.09 %
  • branch
  • 93.23 %
  • cond
  • 79.06 %
  • toggle
  • 86.44 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.150s 271.300us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 18.318us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.910s 17.008us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 63.707us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.950s 89.104us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.260s 60.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.910s 17.008us 1 1 100.00
lc_ctrl_csr_aliasing 0.950s 89.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.060s 380.860us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.040s 688.714us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.890s 12.584us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.480s 33.181us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.510s 3697.860us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_prog_failure 1.480s 33.181us 1 1 100.00
lc_ctrl_errors 9.510s 3697.860us 1 1 100.00
lc_ctrl_security_escalation 4.470s 831.583us 1 1 100.00
lc_ctrl_jtag_state_failure 25.680s 3048.055us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.510s 1411.986us 1 1 100.00
lc_ctrl_jtag_errors 26.260s 5294.992us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 3.750s 638.339us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.410s 1750.075us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.510s 1411.986us 1 1 100.00
lc_ctrl_jtag_errors 26.260s 5294.992us 0 1 0.00
lc_ctrl_jtag_access 2.860s 514.428us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.820s 3538.141us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.510s 350.333us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.320s 58.378us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.840s 1073.794us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.010s 5855.118us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.480s 27.225us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.580s 316.215us 1 1 100.00
lc_ctrl_jtag_alert_test 0.990s 66.934us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 13.060s 679.630us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.850s 24.707us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 12.810s 10969.368us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.820s 22.835us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.060s 177.367us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.060s 177.367us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 18.318us 1 1 100.00
lc_ctrl_csr_rw 0.910s 17.008us 1 1 100.00
lc_ctrl_csr_aliasing 0.950s 89.104us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.470s 100.486us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 18.318us 1 1 100.00
lc_ctrl_csr_rw 0.910s 17.008us 1 1 100.00
lc_ctrl_csr_aliasing 0.950s 89.104us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.470s 100.486us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
lc_ctrl_tl_intg_err 1.850s 77.615us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.850s 77.615us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.040s 688.714us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.070s 447.339us 1 1 100.00
lc_ctrl_sec_cm 6.310s 1007.357us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.470s 831.583us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.060s 380.860us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.410s 1750.075us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.250s 855.739us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.250s 855.739us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.230s 1441.654us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.540s 1134.592us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.540s 1134.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 27.220s 10398.678us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 111192522972020669176596948891624113008945724710934831955138266274635047616041 3118
UVM_INFO @ 5294992079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---