Simulation Results: otbn

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.17 %
  • code
  • 86.24 %
  • assert
  • 90.25 %
  • func
  • 97.03 %
  • block
  • 99.28 %
  • line
  • 99.48 %
  • branch
  • 94.82 %
  • toggle
  • 84.47 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 162.603us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 26.000s 49.901us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 25.000s 44.100us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 28.000s 81.819us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 27.000s 56.168us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 30.000s 44.635us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 25.000s 44.100us 1 1 100.00
otbn_csr_aliasing 27.000s 56.168us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 119.000s 22263.366us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 15.000s 174.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 27.000s 298.097us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 70.000s 213.299us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 52.000s 122.604us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 60.000s 205.946us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 25.000s 129.436us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 24.917us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 19.448us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 29.000s 15.352us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 16.000s 32.891us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 385.966us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 385.966us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 26.000s 49.901us 1 1 100.00
otbn_csr_rw 25.000s 44.100us 1 1 100.00
otbn_csr_aliasing 27.000s 56.168us 1 1 100.00
otbn_same_csr_outstanding 5.000s 18.898us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 26.000s 49.901us 1 1 100.00
otbn_csr_rw 25.000s 44.100us 1 1 100.00
otbn_csr_aliasing 27.000s 56.168us 1 1 100.00
otbn_same_csr_outstanding 5.000s 18.898us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 24.000s 47.341us 1 1 100.00
otbn_dmem_err 29.000s 110.515us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 31.000s 57.876us 1 1 100.00
otbn_controller_ispr_rdata_err 32.000s 108.492us 1 1 100.00
otbn_mac_bignum_acc_err 16.000s 50.680us 0 1 0.00
otbn_urnd_err 6.000s 68.817us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 24.000s 91.837us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 9.000s 19.191us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 22.222us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
otbn_tl_intg_err 12.000s 502.464us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 24.000s 230.498us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 162.603us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 29.000s 110.515us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 24.000s 47.341us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 12.000s 502.464us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 25.000s 129.436us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 24.000s 47.341us 1 1 100.00
otbn_dmem_err 29.000s 110.515us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 24.917us 1 1 100.00
otbn_illegal_mem_acc 24.000s 91.837us 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 24.000s 47.341us 1 1 100.00
otbn_dmem_err 29.000s 110.515us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 24.917us 1 1 100.00
otbn_illegal_mem_acc 24.000s 91.837us 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 25.000s 129.436us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 24.000s 47.341us 1 1 100.00
otbn_dmem_err 29.000s 110.515us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 24.917us 1 1 100.00
otbn_illegal_mem_acc 24.000s 91.837us 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 27.000s 22.830us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 20.032us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 42.000s 123.748us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 42.000s 123.748us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 79.295us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 281.197us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 135.235us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 135.235us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 16.613us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 52.000s 122.604us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 19.974us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 13.723us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 151.000s 3039.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 32.000s 245.789us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 77.376us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_mac_bignum_acc_err 87210068630359911290331049455368888944486526305778403395352684783879706282244 120
UVM_INFO @ 50680451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 11153202009145679759252927358375338944620407885948201873497229837471124489353 164
UVM_INFO @ 245789008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---