Simulation Results: pwrmgr

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.80 %
  • code
  • 95.58 %
  • assert
  • 98.43 %
  • func
  • 96.38 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.47 %
  • toggle
  • 90.96 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.600s 39.890us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.730s 76.228us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.780s 47.200us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.730s 204.395us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.800s 204.109us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.880s 48.786us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.780s 47.200us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 204.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.810s 132.159us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.810s 132.159us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.880s 56.541us 1 1 100.00
pwrmgr_lowpower_invalid 0.640s 69.782us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.700s 85.807us 1 1 100.00
pwrmgr_reset_invalid 0.890s 105.583us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.700s 85.807us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.040s 496.464us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.700s 79.383us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.890s 125.286us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 4.930s 11222.536us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.610s 18.224us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.780s 79.172us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.780s 79.172us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 76.228us 1 1 100.00
pwrmgr_csr_rw 0.780s 47.200us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 204.109us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 131.450us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.730s 76.228us 1 1 100.00
pwrmgr_csr_rw 0.780s 47.200us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 204.109us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 131.450us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.260s 459.364us 1 1 100.00
pwrmgr_sec_cm 1.120s 308.821us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.120s 308.821us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.120s 308.821us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.260s 459.364us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.920s 738.711us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.040s 496.464us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.490s 1387.646us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.750s 104.777us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.760s 39.932us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.120s 308.821us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.120s 308.821us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.120s 308.821us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.570s 42.249us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.630s 54.022us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.820s 127.179us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.780s 47.200us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.780s 47.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.850s 106.306us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3.530s 1869.684us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (pwrmgr_base_vseq.sv:607) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity 1 test run
pwrmgr_stress_all_with_rand_reset 38722060223353382369316172285096126996781788524537919130590157680444813666183 989
UVM_INFO @ 1869683770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 83990475929045182387619373176758879465063235124051685023435895963451038542136 684
UVM_INFO @ 11222535973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---