Simulation Results: rom_ctrl/32kb

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.18 %
  • code
  • 95.50 %
  • assert
  • 97.10 %
  • func
  • 95.94 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 97.92 %
  • toggle
  • 94.31 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.350s 136.402us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.920s 305.407us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.500s 532.940us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.940s 533.571us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.590s 126.956us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.220s 432.025us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.500s 532.940us 1 1 100.00
rom_ctrl_csr_aliasing 3.590s 126.956us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.110s 401.181us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.620s 253.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.640s 170.671us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 16.390s 580.286us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.380s 1129.734us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.120s 526.067us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.240s 399.981us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.240s 399.981us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.920s 305.407us 1 1 100.00
rom_ctrl_csr_rw 3.500s 532.940us 1 1 100.00
rom_ctrl_csr_aliasing 3.590s 126.956us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.600s 534.113us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.920s 305.407us 1 1 100.00
rom_ctrl_csr_rw 3.500s 532.940us 1 1 100.00
rom_ctrl_csr_aliasing 3.590s 126.956us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.600s 534.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.640s 602.474us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 103.750s 396.114us 1 1 100.00
rom_ctrl_tl_intg_err 24.450s 330.258us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 103.750s 396.114us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 103.750s 396.114us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.750s 396.114us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 103.750s 396.114us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.350s 136.402us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.350s 136.402us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.350s 136.402us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.450s 330.258us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
rom_ctrl_kmac_err_chk 7.380s 1129.734us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.230s 3816.530us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.640s 602.474us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.750s 396.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 219.690s 2895.553us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 37998692824816844366179841332247097977090062049871632508815920869831018282397 79
UVM_INFO @ 170670549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---