Simulation Results: rom_ctrl/64kb

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.62 %
  • code
  • 94.38 %
  • assert
  • 97.39 %
  • func
  • 98.09 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 98.37 %
  • toggle
  • 94.95 %
  • FSM
  • 80.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.690s 218.586us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.380s 309.662us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.400s 1583.518us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.870s 1029.421us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.810s 674.568us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.680s 2455.868us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.400s 1583.518us 1 1 100.00
rom_ctrl_csr_aliasing 5.810s 674.568us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.850s 210.479us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.470s 675.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.690s 689.278us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 18.430s 586.111us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.930s 1054.848us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.150s 303.432us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.180s 1025.735us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.180s 1025.735us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.380s 309.662us 1 1 100.00
rom_ctrl_csr_rw 6.400s 1583.518us 1 1 100.00
rom_ctrl_csr_aliasing 5.810s 674.568us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.250s 3113.420us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.380s 309.662us 1 1 100.00
rom_ctrl_csr_rw 6.400s 1583.518us 1 1 100.00
rom_ctrl_csr_aliasing 5.810s 674.568us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.250s 3113.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.860s 765.035us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 458.550s 2244.501us 1 1 100.00
rom_ctrl_tl_intg_err 101.480s 11245.696us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 458.550s 2244.501us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 458.550s 2244.501us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 458.550s 2244.501us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 458.550s 2244.501us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.690s 218.586us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.690s 218.586us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.690s 218.586us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 101.480s 11245.696us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
rom_ctrl_kmac_err_chk 13.930s 1054.848us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.290s 2818.600us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.860s 765.035us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 458.550s 2244.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 173.750s 4421.204us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 94370909236151184079014911677777893694393590644498179470536468023870162786614 79
UVM_INFO @ 689277559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---