Simulation Results: rstmgr

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.63 %
  • code
  • 99.23 %
  • assert
  • 98.39 %
  • func
  • 95.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 98.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.070s 136.573us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.820s 108.908us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.890s 90.824us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.790s 2480.303us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.600s 228.403us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.400s 228.454us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.890s 90.824us 1 1 100.00
rstmgr_csr_aliasing 1.600s 228.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.950s 208.081us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.290s 422.864us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.870s 96.666us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.090s 2078.706us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.090s 2078.706us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.090s 2078.706us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.090s 2078.706us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 12.170s 5571.691us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.790s 63.568us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.180s 200.124us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.180s 200.124us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.820s 108.908us 1 1 100.00
rstmgr_csr_rw 0.890s 90.824us 1 1 100.00
rstmgr_csr_aliasing 1.600s 228.403us 1 1 100.00
rstmgr_same_csr_outstanding 0.830s 79.734us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.820s 108.908us 1 1 100.00
rstmgr_csr_rw 0.890s 90.824us 1 1 100.00
rstmgr_csr_aliasing 1.600s 228.403us 1 1 100.00
rstmgr_same_csr_outstanding 0.830s 79.734us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.170s 16850.452us 1 1 100.00
rstmgr_tl_intg_err 1.890s 504.834us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.170s 16850.452us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.170s 16850.452us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.890s 504.834us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.030s 111.903us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.580s 2565.138us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.080s 302.369us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.170s 16850.452us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 90.824us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.890s 90.824us 1 1 100.00