Simulation Results: rv_timer

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.96 %
  • code
  • 94.66 %
  • assert
  • 98.09 %
  • func
  • 89.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.660s 128.193us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 16.009us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.590s 59.340us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.960s 3114.299us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.730s 76.985us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.700s 48.079us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.590s 59.340us 1 1 100.00
rv_timer_csr_aliasing 0.730s 76.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 3.660s 14752.420us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.400s 2289.223us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 98.660s 117909.526us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 98.660s 117909.526us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.000s 668.065us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 79.402us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.680s 13.715us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.570s 71.409us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.570s 71.409us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 16.009us 1 1 100.00
rv_timer_csr_rw 0.590s 59.340us 1 1 100.00
rv_timer_csr_aliasing 0.730s 76.985us 1 1 100.00
rv_timer_same_csr_outstanding 0.740s 43.931us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 16.009us 1 1 100.00
rv_timer_csr_rw 0.590s 59.340us 1 1 100.00
rv_timer_csr_aliasing 0.730s 76.985us 1 1 100.00
rv_timer_same_csr_outstanding 0.740s 43.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.800s 64.556us 1 1 100.00
rv_timer_tl_intg_err 0.850s 52.193us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.850s 52.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.740s 222.354us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 157.729us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 8.230s 5066.681us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 76013524703730410360961174011743809825745888260486367160754754835642513993021 75
UVM_INFO @ 222353981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 90972967573744803534188048744639694569198709597611244646911554236401701248364 75
UVM_INFO @ 14752420185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 79608957376840121056876232782284722910066561714821271427432821062513913858734 75
UVM_INFO @ 157728838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---