Simulation Results: spi_device/1r1w

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.01 %
  • code
  • 93.90 %
  • assert
  • 95.40 %
  • func
  • 71.73 %
  • line
  • 98.87 %
  • branch
  • 98.18 %
  • cond
  • 95.80 %
  • toggle
  • 87.29 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 44.670s 2989.280us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.150s 99.181us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.720s 387.882us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 28.230s 3354.818us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 12.390s 1823.817us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.160s 108.915us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.720s 387.882us 1 1 100.00
spi_device_csr_aliasing 12.390s 1823.817us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.740s 11.548us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.200s 24.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.720s 71.211us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.930s 4.129us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.780s 15.754us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.200s 1092.411us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.200s 1092.411us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.450s 434.320us 1 1 100.00
spi_device_tpm_sts_read 0.990s 88.051us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 3.240s 805.512us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.620s 876.548us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.100s 2496.703us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.100s 2496.703us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.740s 34.895us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.740s 34.895us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.740s 34.895us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.740s 34.895us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.740s 34.895us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.950s 865.076us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 20.040s 11361.023us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 20.040s 11361.023us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 20.040s 11361.023us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.940s 1009.367us 1 1 100.00
spi_device_read_buffer_direct 3.270s 84.904us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 20.040s 11361.023us 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 265.780s 419508.292us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.920s 230.609us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.920s 230.609us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 2.530s 1896.103us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 44.670s 2989.280us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 62.070s 39514.312us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 359.780s 473970.370us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.770s 13.792us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.840s 15.931us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.600s 38.750us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.600s 38.750us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.150s 99.181us 1 1 100.00
spi_device_csr_rw 1.720s 387.882us 1 1 100.00
spi_device_csr_aliasing 12.390s 1823.817us 1 1 100.00
spi_device_same_csr_outstanding 1.820s 77.925us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.150s 99.181us 1 1 100.00
spi_device_csr_rw 1.720s 387.882us 1 1 100.00
spi_device_csr_aliasing 12.390s 1823.817us 1 1 100.00
spi_device_same_csr_outstanding 1.820s 77.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.950s 39.590us 1 1 100.00
spi_device_tl_intg_err 15.780s 4357.022us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.780s 4357.022us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 53624006127786038766059671738930773664892710902695880706629912862398899725215 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3048582 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3048582 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[982])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 30467431594474623449224552771451545893115076600585220516012022348927452377686 76
UVM_ERROR @ 13466662 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x15b [101011011] vs 0x0 [0])
UVM_ERROR @ 13565662 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x257 [1001010111] vs 0x0 [0])
UVM_ERROR @ 13629662 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x30b [1100001011] vs 0x0 [0])
UVM_ERROR @ 13692662 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3f5 [1111110101] vs 0x0 [0])