Simulation Results: sram_ctrl/main

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.00 %
  • code
  • 95.66 %
  • assert
  • 97.96 %
  • func
  • 91.40 %
  • block
  • 96.03 %
  • line
  • 96.75 %
  • branch
  • 94.17 %
  • toggle
  • 91.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 703.849us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 21.540us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.844us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 384.267us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 97.685us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 375.485us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 37.844us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 97.685us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 106.000s 11138.644us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 52.000s 11047.055us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 27.000s 12106.336us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 89.000s 14745.680us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 138.000s 15480.517us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 22.000s 20860.609us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 29.000s 13436.221us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 30.000s 17552.436us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 694.546us 1 1 100.00
sram_ctrl_partial_access_b2b 161.000s 5389.355us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 4397.348us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 666.772us 0 1 0.00
sram_ctrl_throughput_w_readback 6.000s 2737.351us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1944.022us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 365.910us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 379.000s 374779.482us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.692us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 141.814us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 141.814us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.540us 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.844us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 97.685us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 88.853us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.540us 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.844us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 97.685us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 88.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 7394.243us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 268.571us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 2771.436us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 268.571us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 2771.436us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1944.022us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1944.022us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.844us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 30.000s 17552.436us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 17552.436us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 17552.436us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 29.000s 13436.221us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 1333.608us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 7394.243us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 1414.475us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 703.849us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 703.849us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 30.000s 17552.436us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 268.571us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 29.000s 13436.221us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 268.571us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 268.571us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 703.849us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 268.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.000s 5276.974us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 26569452820840213559021526953563884012295398021415747886661939148553405442803 86
UVM_INFO @ 4397347521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 77163289952931597437847896469367953165111016791701845159821922050744602538577 86
UVM_INFO @ 666772220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 9934309817328931074508051519656699516358128137738264871607147604452548647311 86
UVM_INFO @ 2737350792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---