Simulation Results: sysrst_ctrl

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.54 %
  • code
  • 94.15 %
  • assert
  • 96.07 %
  • func
  • 66.40 %
  • line
  • 97.92 %
  • branch
  • 97.89 %
  • cond
  • 95.43 %
  • toggle
  • 100.00 %
  • FSM
  • 79.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.380s 2128.658us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.050s 2470.231us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.100s 2291.129us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.530s 2544.787us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.770s 4033.058us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.280s 2090.488us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 39.170s 75835.860us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.070s 2695.699us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 3.060s 2115.719us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.280s 2090.488us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.070s 2695.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 12.680s 46453.234us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 60.490s 76043.512us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.800s 3491.173us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 5.940s 3211.789us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.720s 2545.528us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.430s 2072.440us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 5.150s 3907.510us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.660s 2627.126us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.920s 2946.891us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 34.110s 39390.285us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 5.010s 6735.656us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.780s 2009.773us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.690s 2031.171us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.350s 2072.602us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.350s 2072.602us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.770s 4033.058us 1 1 100.00
sysrst_ctrl_csr_rw 1.280s 2090.488us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.070s 2695.699us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.510s 4512.558us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.770s 4033.058us 1 1 100.00
sysrst_ctrl_csr_rw 1.280s 2090.488us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.070s 2695.699us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.510s 4512.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 36.940s 22013.249us 1 1 100.00
sysrst_ctrl_tl_intg_err 39.450s 22209.616us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 39.450s 22209.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 13.180s 7203.629us 1 1 100.00