Simulation Results: uart

 
20/07/2026 15:30:33 DVSim: v1.49.12 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.83 %
  • code
  • 95.99 %
  • assert
  • 98.56 %
  • func
  • 50.94 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.80 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 11.860s 6211.005us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.670s 112.707us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 131.559us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.120s 526.503us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.950s 48.991us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.090s 24.616us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 131.559us 1 1 100.00
uart_csr_aliasing 0.950s 48.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 37.560s 44171.142us 1 1 100.00
parity 2 2 100.00
uart_smoke 11.860s 6211.005us 1 1 100.00
uart_tx_rx 37.560s 44171.142us 1 1 100.00
parity_error 2 2 100.00
uart_intr 3.310s 11429.832us 1 1 100.00
uart_rx_parity_err 19.690s 20639.655us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 37.560s 44171.142us 1 1 100.00
uart_intr 3.310s 11429.832us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 23.020s 57822.054us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 14.530s 88686.345us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 12.500s 24810.497us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 3.310s 11429.832us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 3.310s 11429.832us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 3.310s 11429.832us 1 1 100.00
perf 1 1 100.00
uart_perf 98.320s 24346.911us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.110s 1352.414us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.110s 1352.414us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 13.200s 24031.386us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.370s 5699.783us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.880s 4492.325us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.000s 4378.813us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 210.520s 159333.252us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 34.750s 88150.159us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.650s 77.551us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.620s 60.627us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.730s 264.257us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.730s 264.257us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.670s 112.707us 1 1 100.00
uart_csr_rw 0.630s 131.559us 1 1 100.00
uart_csr_aliasing 0.950s 48.991us 1 1 100.00
uart_same_csr_outstanding 0.670s 50.636us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.670s 112.707us 1 1 100.00
uart_csr_rw 0.630s 131.559us 1 1 100.00
uart_csr_aliasing 0.950s 48.991us 1 1 100.00
uart_same_csr_outstanding 0.670s 50.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.910s 233.659us 1 1 100.00
uart_tl_intg_err 1.210s 176.043us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.210s 176.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 17.200s 1935.942us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 83149085850610367855308278094106196573927073154826843550320124179237138472234 76
UVM_ERROR @ 21557025558 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 21557045558 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 21559105558 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 21559105558 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0