Simulation Results: adc_ctrl

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.46 %
  • code
  • 91.74 %
  • assert
  • 91.73 %
  • func
  • 12.92 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 86.23 %
  • toggle
  • 99.76 %
  • FSM
  • 78.38 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 8.030s 5876.938us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.100s 1242.480us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.970s 489.245us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 12.800s 40837.170us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.030s 1057.203us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.080s 582.159us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.970s 489.245us 1 1 100.00
adc_ctrl_csr_aliasing 3.030s 1057.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.170s 471.473us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.770s 392.034us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.770s 364.249us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.970s 296.591us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.720s 389.937us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.750s 458.034us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.740s 477.610us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.690s 304.552us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.420s 4321.934us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 10.660s 32186.371us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 30.530s 73229.918us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 0.960s 903.934us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.720s 438.054us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.810s 375.375us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.470s 983.950us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.470s 983.950us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.100s 1242.480us 1 1 100.00
adc_ctrl_csr_rw 0.970s 489.245us 1 1 100.00
adc_ctrl_csr_aliasing 3.030s 1057.203us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.200s 2186.362us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.100s 1242.480us 1 1 100.00
adc_ctrl_csr_rw 0.970s 489.245us 1 1 100.00
adc_ctrl_csr_aliasing 3.030s 1057.203us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.200s 2186.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 10.050s 7835.673us 1 1 100.00
adc_ctrl_tl_intg_err 4.690s 8422.892us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.690s 8422.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.110s 951.675us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 86264322344100275259773048141211395415821199346420978117126239606404221045790 386
UVM_INFO @ 471473369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 84121668770631068408912643726381696859017732236402405535941923680740453993790 386
UVM_INFO @ 392034350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 89351678605515712663068940232791605462056957737395055068225872547451647946382 386
UVM_INFO @ 364248568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 104597575970211309229650627319727950512488628042627390491460132686203313032555 386
UVM_INFO @ 296591372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 83623698788147670062379240243004256997346437588643148876689744056192316879070 386
UVM_INFO @ 389937495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 28535631589386201061992186010257321226984644147455803059627678079730855888494 386
UVM_INFO @ 458034482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 99807642906928448708353997261175730475849783151716028596123656828493288529282 386
UVM_INFO @ 304551930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 48229550970085847124868996225475475034150111806278065557821065612223561034078 386
UVM_INFO @ 477610159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 26185372725938225086560186325061919208859699691161813048011179531341304655412 399
UVM_INFO @ 951674945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 3437817551431511006617048993491883815928237479986136579862750863933541519364 387
UVM_INFO @ 903934209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---