Simulation Results: aes/masked

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.56 %
  • code
  • 93.85 %
  • assert
  • 98.23 %
  • func
  • 73.61 %
  • block
  • 94.52 %
  • line
  • 96.27 %
  • branch
  • 87.81 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 177.042us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 82.500us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 55.705us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 70.933us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 9.000s 11936.896us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 1465.689us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 88.183us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 70.933us 1 1 100.00
aes_csr_aliasing 2.000s 1465.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 82.500us 1 1 100.00
aes_config_error 2.000s 357.641us 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 82.500us 1 1 100.00
aes_config_error 2.000s 357.641us 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 796.255us 1 1 100.00
aes_b2b 7.000s 430.508us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 82.500us 1 1 100.00
aes_config_error 2.000s 357.641us 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
aes_alert_reset 3.000s 183.693us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 94.586us 1 1 100.00
aes_config_error 2.000s 357.641us 1 1 100.00
aes_alert_reset 3.000s 183.693us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 8.000s 499.672us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 22.000s 1873.692us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 183.693us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 796.255us 1 1 100.00
aes_sideload 6.000s 235.188us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 8.000s 468.415us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 34.000s 1965.350us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 130.866us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 224.970us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 224.970us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.705us 1 1 100.00
aes_csr_rw 1.000s 70.933us 1 1 100.00
aes_csr_aliasing 2.000s 1465.689us 1 1 100.00
aes_same_csr_outstanding 3.000s 146.547us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.705us 1 1 100.00
aes_csr_rw 1.000s 70.933us 1 1 100.00
aes_csr_aliasing 2.000s 1465.689us 1 1 100.00
aes_same_csr_outstanding 3.000s 146.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 95.991us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_cipher_fi 3.000s 91.538us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 61.224us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 61.224us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 61.224us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 61.224us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 172.727us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 7.000s 1307.809us 1 1 100.00
aes_tl_intg_err 2.000s 122.438us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 122.438us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 183.693us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 61.224us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 61.224us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 82.500us 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
aes_alert_reset 3.000s 183.693us 1 1 100.00
aes_core_fi 2.000s 208.766us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 357.641us 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
aes_core_fi 2.000s 208.766us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 61.224us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 88.082us 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 796.255us 1 1 100.00
aes_sideload 6.000s 235.188us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 88.082us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 88.082us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 88.082us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 88.082us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 88.082us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 796.255us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 422.265us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_cipher_fi 3.000s 91.538us 1 1 100.00
aes_ctr_fi 2.000s 155.872us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 422.265us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_cipher_fi 3.000s 91.538us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 91.538us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 422.265us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_ctr_fi 2.000s 155.872us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 422.265us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_cipher_fi 3.000s 91.538us 1 1 100.00
aes_ctr_fi 2.000s 155.872us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 183.693us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_cipher_fi 3.000s 91.538us 1 1 100.00
aes_ctr_fi 2.000s 155.872us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_cipher_fi 3.000s 91.538us 1 1 100.00
aes_ctr_fi 2.000s 155.872us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_ctr_fi 2.000s 155.872us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 422.265us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 422.265us 0 1 0.00
aes_control_fi 2.000s 54.986us 1 1 100.00
aes_cipher_fi 3.000s 91.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 650.355us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 41708984884907754316069615211295754436934597316448674290969306279952538193754 5371
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 42369099479345111246019055760412414837365754960013015090104588743182694780797 176935
UVM_INFO @ 1965349931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 31472040971668788732425245526411809167143001590241599503308656201127029458509 533
UVM_INFO @ 650355406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---