Simulation Results: chip

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.30 %
  • code
  • 83.61 %
  • assert
  • 97.12 %
  • func
  • 33.18 %
  • line
  • 93.98 %
  • branch
  • 92.46 %
  • cond
  • 87.93 %
  • toggle
  • 86.55 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
75.45%
V2S
50.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 183.580s 3692.445us 1 1 100.00
chip_sw_example_rom 89.370s 2740.715us 1 1 100.00
chip_sw_example_manufacturer 162.480s 3088.835us 1 1 100.00
chip_sw_example_concurrency 159.150s 2630.999us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 355.630s 10178.627us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 357.440s 6119.382us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 404.630s 5353.752us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3352.750s 28223.596us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 97.150s 3289.305us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3352.750s 28223.596us 1 1 100.00
chip_csr_rw 357.440s 6119.382us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.470s 44.094us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 306.750s 4513.371us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 306.750s 4513.371us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 306.750s 4513.371us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 395.410s 4266.811us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 395.410s 4266.811us 1 1 100.00
chip_sw_uart_tx_rx_idx1 394.470s 4345.675us 1 1 100.00
chip_sw_uart_tx_rx_idx2 385.490s 5248.734us 1 1 100.00
chip_sw_uart_tx_rx_idx3 433.330s 4404.516us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 927.510s 8558.555us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 388.460s 4178.260us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1094.250s 14434.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 204.380s 5653.496us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 204.380s 5653.496us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 203.100s 4118.205us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 145.640s 3303.755us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 254.880s 4611.861us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 139.230s 3899.525us 1 1 100.00
chip_tap_straps_testunlock0 326.710s 6119.131us 1 1 100.00
chip_tap_straps_rma 341.430s 6698.853us 1 1 100.00
chip_tap_straps_prod 1103.200s 15886.989us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 388.440s 5143.354us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 388.440s 5143.354us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 707.690s 8590.911us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1114.300s 10680.826us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 354.210s 4771.451us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 627.040s 6177.477us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4216.060s 18554.134us 1 1 100.00
chip_sw_aes_enc_jitter_en 171.150s 3217.164us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 805.770s 7580.387us 1 1 100.00
chip_sw_hmac_enc_jitter_en 162.130s 3440.393us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1458.910s 12566.499us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 226.730s 3683.545us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 396.770s 5647.000us 1 1 100.00
chip_sw_clkmgr_jitter 201.690s 3204.368us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 252.250s 4122.133us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 550.240s 7920.111us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 261.030s 5276.698us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 163.840s 3242.361us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 261.030s 5276.698us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 152.930s 3409.054us 1 1 100.00
chip_sw_aes_smoketest 200.750s 3608.392us 1 1 100.00
chip_sw_aon_timer_smoketest 242.170s 3815.696us 1 1 100.00
chip_sw_clkmgr_smoketest 226.910s 4356.180us 1 1 100.00
chip_sw_csrng_smoketest 150.930s 3660.292us 1 1 100.00
chip_sw_entropy_src_smoketest 916.070s 8011.089us 1 1 100.00
chip_sw_gpio_smoketest 192.850s 3498.342us 1 1 100.00
chip_sw_hmac_smoketest 220.080s 3800.347us 1 1 100.00
chip_sw_kmac_smoketest 229.540s 3454.911us 1 1 100.00
chip_sw_otbn_smoketest 1563.700s 10579.132us 1 1 100.00
chip_sw_pwrmgr_smoketest 357.680s 7250.145us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 422.100s 7538.388us 1 1 100.00
chip_sw_rv_plic_smoketest 165.380s 2866.499us 1 1 100.00
chip_sw_rv_timer_smoketest 162.780s 2741.881us 1 1 100.00
chip_sw_rstmgr_smoketest 187.770s 3657.500us 1 1 100.00
chip_sw_sram_ctrl_smoketest 189.610s 4286.816us 1 1 100.00
chip_sw_uart_smoketest 163.410s 3256.347us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 155.580s 3907.360us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 472.830s 6963.953us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7638.660s 60025.612us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3112.480s 15870.350us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 48.293s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1142.670s 15050.693us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 1061.350s 14960.158us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7130.460s 55926.477us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7365.870s 56419.417us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 81.820s 2616.616us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 81.820s 2616.616us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3352.750s 28223.596us 1 1 100.00
chip_same_csr_outstanding 1536.340s 14832.566us 1 1 100.00
chip_csr_hw_reset 355.630s 10178.627us 1 1 100.00
chip_csr_rw 357.440s 6119.382us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3352.750s 28223.596us 1 1 100.00
chip_same_csr_outstanding 1536.340s 14832.566us 1 1 100.00
chip_csr_hw_reset 355.630s 10178.627us 1 1 100.00
chip_csr_rw 357.440s 6119.382us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 32.060s 586.366us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 6.090s 39.781us 1 1 100.00
xbar_smoke_large_delays 51.530s 9772.305us 1 1 100.00
xbar_smoke_slow_rsp 47.930s 4337.435us 1 1 100.00
xbar_random_zero_delays 16.260s 193.365us 1 1 100.00
xbar_random_large_delays 131.960s 22178.976us 1 1 100.00
xbar_random_slow_rsp 103.220s 11131.361us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 32.410s 1069.720us 1 1 100.00
xbar_error_and_unmapped_addr 7.580s 210.635us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 16.000s 272.307us 1 1 100.00
xbar_error_and_unmapped_addr 7.580s 210.635us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 19.250s 281.677us 1 1 100.00
xbar_access_same_device_slow_rsp 217.650s 27318.887us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 17.900s 292.144us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 46.970s 920.100us 1 1 100.00
xbar_stress_all_with_error 146.650s 2844.112us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 171.490s 874.028us 1 1 100.00
xbar_stress_all_with_reset_error 141.880s 706.447us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3112.480s 15870.350us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 494.630s 9199.689us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 464.360s 7884.936us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 49.280s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 67.373s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 56.611s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 48.305s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 84.787s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 61.754s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 67.441s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 65.778s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 61.147s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 67.211s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 61.489s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 82.961s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 161.409s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 74.533s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 79.929s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 25.750s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 20.920s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 25.200s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 21.590s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 28.880s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.870s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20.960s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 21.170s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 21.940s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 22.490s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 20.430s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 22.710s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 23.130s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 20.480s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 21.000s 10.340us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 206.847s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 146.898s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 28.893s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 7.779s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 78.117s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 6207.560s 28762.011us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3295.190s 20088.378us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6221.900s 31469.393us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3488.010s 17115.244us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3136.350s 35241.389us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3136.350s 35241.389us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 241.410s 4322.919us 1 1 100.00
chip_sw_aes_enc_jitter_en 171.150s 3217.164us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 167.970s 2946.941us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 212.320s 3410.573us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 941.500s 7536.270us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 191.440s 3993.854us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 382.560s 5899.249us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 375.260s 6261.710us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 466.660s 5960.032us 1 1 100.00
chip_plic_all_irqs_10 341.770s 4803.418us 1 1 100.00
chip_plic_all_irqs_20 379.530s 3946.633us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 204.210s 2858.147us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1226.030s 18659.506us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 353.930s 5366.318us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 200.740s 4251.011us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.142s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 768.730s 6954.093us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1217.350s 8292.041us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 921.570s 8532.428us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9406.990s 255685.478us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 313.520s 4964.301us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 357.680s 7250.145us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 313.520s 4964.301us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 448.790s 8275.493us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 448.790s 8275.493us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 306.430s 8686.321us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 444.030s 5890.523us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 636.390s 6188.880us 1 1 100.00
chip_sw_aes_idle 212.320s 3410.573us 1 1 100.00
chip_sw_hmac_enc_idle 219.220s 3916.551us 1 1 100.00
chip_sw_kmac_idle 216.530s 3983.805us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 404.940s 6555.294us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 344.850s 6202.196us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 286.520s 6213.783us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 331.290s 4461.443us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 774.210s 12143.467us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 410.950s 4820.412us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 423.660s 5020.491us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 446.670s 4978.657us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 394.000s 5088.010us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 411.180s 4608.572us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 452.220s 5992.407us 1 1 100.00
chip_sw_ast_clk_outputs 707.690s 8590.911us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 407.470s 8968.470us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 446.670s 4978.657us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 394.000s 5088.010us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 354.210s 4771.451us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 627.040s 6177.477us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4216.060s 18554.134us 1 1 100.00
chip_sw_aes_enc_jitter_en 171.150s 3217.164us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 805.770s 7580.387us 1 1 100.00
chip_sw_hmac_enc_jitter_en 162.130s 3440.393us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1458.910s 12566.499us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 226.730s 3683.545us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 396.770s 5647.000us 1 1 100.00
chip_sw_clkmgr_jitter 201.690s 3204.368us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 164.290s 3603.026us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 380.130s 6052.522us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 668.020s 8198.846us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4206.060s 25363.365us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 192.190s 3491.372us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 146.490s 3235.813us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1517.710s 15445.585us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 191.250s 3482.925us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 431.740s 6683.447us 1 1 100.00
chip_sw_flash_init_reduced_freq 1402.820s 29771.918us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2521.650s 20461.928us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 707.690s 8590.911us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 387.010s 4741.604us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 256.000s 4275.181us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 375.260s 6261.710us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 768.730s 6954.093us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2341.480s 25164.681us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 348.000s 5005.383us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 523.390s 7759.375us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 183.700s 4091.395us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2370.980s 15057.978us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 202.290s 3960.568us 1 1 100.00
chip_sw_edn_entropy_reqs 633.890s 8022.458us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 202.290s 3960.568us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2341.480s 25164.681us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 197.370s 3629.171us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1382.260s 26984.187us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 516.510s 5821.438us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 627.040s 6177.477us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 432.840s 4516.972us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 354.210s 4771.451us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3656.920s 44584.072us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1382.260s 26984.187us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 206.860s 3840.210us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1487.320s 11770.562us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.980s 3339.937us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3656.920s 44584.072us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.980s 3339.937us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.980s 3339.937us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.980s 3339.937us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 211.980s 3339.937us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 375.260s 6261.710us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 564.450s 16828.403us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 524.690s 6126.335us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 436.040s 5231.375us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 436.040s 5231.375us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 161.130s 3878.689us 1 1 100.00
chip_sw_hmac_enc_jitter_en 162.130s 3440.393us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 219.220s 3916.551us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1106.590s 8697.418us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1920.530s 12018.730us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 398.200s 4739.928us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 466.010s 5910.563us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 391.650s 4954.333us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 286.710s 3785.059us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1487.320s 11770.562us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1458.910s 12566.499us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 773.610s 6338.014us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 941.500s 7536.270us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4055.470s 20018.397us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 181.290s 3102.331us 1 1 100.00
chip_sw_kmac_mode_kmac 176.030s 3614.604us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 226.730s 3683.545us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1487.320s 11770.562us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 743.400s 12038.272us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 173.230s 2878.969us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 859.440s 7235.952us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 216.530s 3983.805us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 382.560s 5899.249us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 139.230s 3899.525us 1 1 100.00
chip_tap_straps_rma 341.430s 6698.853us 1 1 100.00
chip_tap_straps_prod 1103.200s 15886.989us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 182.170s 4176.186us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 743.400s 12038.272us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 743.400s 12038.272us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 743.400s 12038.272us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 738.180s 7458.809us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 211.980s 3339.937us 0 1 0.00
chip_sw_flash_rma_unlocked 3656.920s 44584.072us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 208.720s 4377.436us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 611.520s 9086.297us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 599.990s 9544.252us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 760.350s 10033.459us 0 1 0.00
chip_sw_lc_ctrl_transition 743.400s 12038.272us 1 1 100.00
chip_sw_keymgr_key_derivation 1487.320s 11770.562us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 382.720s 9368.662us 1 1 100.00
chip_sw_sram_ctrl_execution_main 697.440s 11805.202us 1 1 100.00
chip_prim_tl_access 564.450s 16828.403us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 407.470s 8968.470us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 410.950s 4820.412us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 423.660s 5020.491us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 446.670s 4978.657us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 394.000s 5088.010us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 411.180s 4608.572us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 452.220s 5992.407us 1 1 100.00
chip_tap_straps_dev 139.230s 3899.525us 1 1 100.00
chip_tap_straps_rma 341.430s 6698.853us 1 1 100.00
chip_tap_straps_prod 1103.200s 15886.989us 1 1 100.00
chip_rv_dm_lc_disabled 70.890s 2606.467us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 146.800s 3828.310us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 107.350s 3771.590us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 110.860s 3772.312us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 91.350s 3492.149us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 2039.150s 39559.492us 1 1 100.00
chip_rv_dm_lc_disabled 70.890s 2606.467us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 802.340s 11923.107us 0 1 0.00
chip_sw_lc_walkthrough_prod 597.280s 9536.204us 0 1 0.00
chip_sw_lc_walkthrough_prodend 965.700s 15343.800us 1 1 100.00
chip_sw_lc_walkthrough_rma 1135.820s 26002.571us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2039.150s 39559.492us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 113.480s 3197.758us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 93.160s 2980.188us 1 1 100.00
rom_volatile_raw_unlock 51.344s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4156.090s 17833.833us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4216.060s 18554.134us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 636.390s 6188.880us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 636.390s 6188.880us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 636.390s 6188.880us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 328.790s 4415.781us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 743.400s 12038.272us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1382.260s 26984.187us 1 1 100.00
chip_sw_otbn_mem_scramble 328.790s 4415.781us 1 1 100.00
chip_sw_keymgr_key_derivation 1487.320s 11770.562us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 355.690s 6140.874us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 188.410s 3697.664us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1382.260s 26984.187us 1 1 100.00
chip_sw_otbn_mem_scramble 328.790s 4415.781us 1 1 100.00
chip_sw_keymgr_key_derivation 1487.320s 11770.562us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 355.690s 6140.874us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 188.410s 3697.664us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 743.400s 12038.272us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 340.090s 5356.644us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 182.170s 4176.186us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 208.720s 4377.436us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 611.520s 9086.297us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 599.990s 9544.252us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 760.350s 10033.459us 0 1 0.00
chip_sw_lc_ctrl_transition 743.400s 12038.272us 1 1 100.00
chip_prim_tl_access 564.450s 16828.403us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 564.450s 16828.403us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 825.880s 8457.307us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 104.340s 3075.869us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1204.260s 27035.616us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 264.790s 7410.022us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 420.660s 9338.905us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 564.950s 9823.561us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1045.020s 23290.867us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 316.580s 6599.324us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 448.790s 8275.493us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1042.580s 16926.128us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 401.930s 5705.890us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 104.340s 3075.869us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 359.350s 5987.121us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1051.070s 23521.313us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 393.330s 8242.856us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 149.180s 2782.606us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 257.000s 6451.042us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 805.310s 10156.402us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1388.500s 17378.646us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2142.960s 29695.306us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 258.130s 3933.895us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 375.260s 6261.710us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 382.720s 9368.662us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 382.720s 9368.662us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1388.500s 17378.646us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 257.000s 6451.042us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 401.930s 5705.890us 1 1 100.00
chip_sw_pwrmgr_smoketest 357.680s 7250.145us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 283.610s 5183.824us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 499.860s 7089.047us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 295.670s 4531.271us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1226.030s 18659.506us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 146.060s 3532.230us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 375.260s 6261.710us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1217.350s 8292.041us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 482.760s 5912.507us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 504.500s 5659.763us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 212.830s 3749.747us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 188.410s 3697.664us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 499.860s 7089.047us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 499.860s 7089.047us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 148.360s 3254.778us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1137.370s 16254.453us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 939.840s 14162.399us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 283.610s 5183.824us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 206.070s 3911.347us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1516.510s 13292.909us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 341.430s 6698.853us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 70.890s 2606.467us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 466.660s 5960.032us 1 1 100.00
chip_plic_all_irqs_10 341.770s 4803.418us 1 1 100.00
chip_plic_all_irqs_20 379.530s 3946.633us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 177.670s 3724.179us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 179.200s 3391.824us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3112.480s 15870.350us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 216.280s 3942.359us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 225.390s 3443.711us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 221.900s 3603.695us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 196.430s 3724.738us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 355.690s 6140.874us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 396.770s 5647.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 501.700s 8714.977us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 411.900s 8087.385us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 697.440s 11805.202us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 375.260s 6261.710us 1 1 100.00
chip_sw_data_integrity_escalation 388.440s 5143.354us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 805.310s 10156.402us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1187.550s 24562.866us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 190.140s 3160.536us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 241.500s 4303.563us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 324.020s 5001.979us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1187.550s 24562.866us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1187.550s 24562.866us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2472.740s 20473.632us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2472.740s 20473.632us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 405.780s 8442.258us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3136.350s 35241.389us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 154.540s 3061.283us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 137.590s 3106.826us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 272.060s 4145.429us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 383.350s 4425.080us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1015.900s 8652.650us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5696.740s 32490.704us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1891.450s 12477.757us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 168.500s 3466.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 209.410s 2632.411us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 181.020s 3777.870us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9650.290s 69449.657us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1119.740s 7024.405us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 552.300s 8171.097us 0 1 0.00
rom_e2e_jtag_debug_dev 465.990s 7449.438us 0 1 0.00
rom_e2e_jtag_debug_rma 706.920s 14289.229us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 99.220s 3335.549us 0 1 0.00
rom_e2e_jtag_inject_dev 102.210s 2772.421us 0 1 0.00
rom_e2e_jtag_inject_rma 235.230s 5173.008us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 49.828s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 286.020s 4307.221us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 316.450s 3000.629us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 744.720s 5661.354us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 827.940s 7039.515us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 271.210s 3216.349us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 661.510s 5422.895us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 174.120s 3718.331us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 168.440s 3031.383us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 270.580s 7882.909us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 281.880s 6039.202us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1388.500s 17378.646us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 552.300s 8171.097us 0 1 0.00
rom_e2e_jtag_debug_dev 465.990s 7449.438us 0 1 0.00
rom_e2e_jtag_debug_rma 706.920s 14289.229us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 464.290s 6007.872us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 375.260s 6261.710us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5790.920s 38496.906us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5790.920s 38496.906us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 170.390s 4011.355us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 395.410s 4266.811us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3398.820s 20047.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 235.190s 3901.494us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 20.050s 10.220us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 7.410s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 151.410s 3451.336us 1 1 100.00
chip_sw_otp_ctrl_descrambling 216.450s 3694.390us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 275.590s 4693.433us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.183s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 255.600s 4207.832us 1 1 100.00
ate_bootstrap_flash_erase 571.480s 10010.160us 0 1 0.00
ate_bootstrap_one_frame 6255.400s 43377.201us 1 1 100.00
ate_bootstrap_disjoint 9564.630s 79476.032us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 110216678605657496609772577313330577222154831008656285564517305637726606895564 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 107411381091696873364356374945088688367388841173986488909988120428244448913586 None
---- STDERR ----
Another command (pid=375444) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 109974083547084307138020116655563011735778604882784891903648218179538225731046 None
Another command (pid=487971) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=576688) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=578908) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 60140237355779617239945718190099623073844180122835556476373416923504568761909 None
Another command (pid=417579) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=407420) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=564807) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 86148746744101691261436102136565264571035944541134045750140052994458682152845 None
Another command (pid=473211) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=470793) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=417579) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 99390655476025573240463231520460121673071014985323368906461716491971034838429 None
Another command (pid=731955) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=715988) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=720476) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 186775367437632157417786426961511766837305375719222260449496563581943767564 None
Another command (pid=419211) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=393515) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=379528) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 104233717156332044795584394830421827404783841165448163320745839380647645487629 None
Another command (pid=417579) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=407420) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=453881) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 59447936234119365787031919440411914214131494651538945935282121361562820665103 None
Another command (pid=470793) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=474411) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=417579) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 62239415964544614843589378297322139554040752132636314845693150753639874628846 None
---- STDERR ----
Another command (pid=471207) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=472043) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 23479806924824765355277084080893248239545984233813776886672178422452507670753 None
Another command (pid=407420) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=564807) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=465703) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 90847139513285609627351110584060122539880045298192559785563340806736365191302 None
---- STDERR ----
Another command (pid=379528) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 32559939061088968650813376016417890980808620951961048130429258059602584898441 None
Another command (pid=489494) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=578908) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=577115) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 9269097609923350268871372932861955290710036693609414594341544787510503507743 None
Another command (pid=772500) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=765387) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=765779) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 114184420263513176471762174723509845318672262888184682248819638286560218545606 None
Another command (pid=489383) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=473211) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=470793) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 63777092307267292305214062095772573824297345658528760407264957749879694279665 None
Another command (pid=591441) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=589177) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=594432) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 16295141983713591641999631030114834058746691162413567626244489233599300293451 None
Another command (pid=563861) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=657147) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=624535) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 34115883261871711892071446918025412967642927650623264920112850280931374368667 None
Another command (pid=668982) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=683980) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=670046) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 29992449308190170074203232531124944281605036011649161163526276748876406058323 None
Another command (pid=453426) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=393515) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=379528) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 105588356821787395867642047536689829826788420710253174713926976643082031402892 None
---- STDERR ----
Another command (pid=380233) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=434255) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 105675646591680549292468769595984579074376322738639920768610068326937541039264 None
Another command (pid=474411) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=417579) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=489165) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 51020953695686640009010873232674196886459409276643092685001318411506470848263 None
Another command (pid=393515) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=379528) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=426817) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 58658293252177371379411092050935689799249185053365295785479587278353165782099 None
Another command (pid=375444) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=393840) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=380233) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 73585086497978127605754449849947521712101280953102678558322551529779994416727 None
Another command (pid=393840) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=380233) is running. Waiting for it to complete on the server (server_pid=280376)...
Another command (pid=434255) is running. Waiting for it to complete on the server (server_pid=280376)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 5504688263514860571062984642341249235006075003186085373658987007943475838576 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 46661734057372660970142157311454313682165384529611858490204984152631391831231 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 109001016210746662732240610971634662177689588859871114143750764485859693331419 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 822075057389980087658317070526841080258810832452929299803172699111352516181 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 32913043436018390059883893839943452862562165642099304690604541482516524065585 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 75318105161989027320850691950220928355593495295914725817894404276597235569431 310
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 55175318342302395473673678643063906691777519705761691840771137687674183134107 368
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 40746128739181759287716250275473643845646332359924949067681828899200479547871 367
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 48893403462401556125816651940500888573937159283463869011627304026328615051376 365
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 74926805029357136061617183490648990251811212486758918063883017260384534999093 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 31142352307509376146805107935734641386410648769281020774231864155329575902775 328
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 38642275402128307759007131923327552158985216512472547016065566392390887085621 328
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 4 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 24913428706245624784483039342812002982460946983570114357815856973809507880091 315
UVM_ERROR @ 6451.042000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6451.042000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 45945228908303010042505030481570547393238430116292461472282852137872371421891 314
UVM_ERROR @ 6599.324000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6599.324000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 92820015496671359845178024951356440205991642770090224231133417092607216338936 325
UVM_ERROR @ 9338.904500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9338.904500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 29570918605856214436814755362888287029325420117847986648378699319851553311016 319
UVM_ERROR @ 8275.493000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8275.493000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 39525946036227582337002310844337196089831745189354281138717326251640292554463 327
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 44201401920624192333385440775947524382849473959428105746696265177182429183301 328
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 50512376784042296037810537907441354425593019090911969028543008569599131716430 325
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 2 test runs
chip_sw_lc_walkthrough_dev 105796893898256198453775595786534109580241623341559993055534061872778852179638 369
UVM_INFO @ 11923.107368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 82535338437158215558400047505751950793517252230853873067565263993481521260987 369
UVM_INFO @ 9536.203604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 46618359881347165935484428964440949773355876499881764945104886045642077145189 313
UVM_ERROR @ 2782.605964 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2782.605964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 40898370394489068693523493716372336770666882335675804791393508268070094380631 354
UVM_ERROR @ 23521.313131 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 23521.313131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 85507404537232633221132824170374887390514595154505835306735989487724287834161 377
UVM_INFO @ 12018.730192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 89715489122336830687859358940825145393993271714319513203692584479004720274576 334
UVM_INFO @ 20018.397133 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 94627914022243427907939739911540052576551065653327939106853749032977461589379 217
TL item was: req: (cip_tl_seq_item@31580) { a_addr: 'h10378 a_data: 'h68bf25bf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h18aff d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2616.615536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 13589485067855950535494463515113778258327977574002520140597927061622699777321 224
TL item was: req: (cip_tl_seq_item@30258) { a_addr: 'h10460 a_data: 'h841288f6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h1a5c0 d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3289.305048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 113851858413447931706154923545776453736082682522963148110592835035441468242202 362
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 109335913294961343432733949402713344852376010977792698094630630590724391604805 325
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 102184051459201150148273479973501431873353739577432882479950601885705782972098 366
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 89351869538235596729293434545082997597545821066094489727627187192230672735904 328
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 27778692861239894580989792092368990959408920155658719922292514390427737196548 301
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 9523858796408467638288420446272296294510519146257156807004214506662235964659 451
UVM_INFO @ 4118.205000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 1989780202451375483115078364087996104548900743978943896952753859603340338688 327
UVM_INFO @ 3443.711499 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 44943670731733185436486178889251779602441414669156559658408651465031975365660 309
UVM_INFO @ 3339.936660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 29618355076639314185546369172945432246251758677268567215051557994640524715646 342
UVM_INFO @ 10033.459392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 74464656882592917780056725814032446189622525950967741681150629224390890606169 316
UVM_ERROR @ 3031.382622 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3031.382622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 40670820177103264333241463816347506599492343606529649898783767634770818975479 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_rma 114359237306627406815492057290935841835402977075125896983896364630000521196737 308
UVM_INFO @ 26002.570920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 85898704737337689246022649290814742409880395949241212587966013710562553478168 303
UVM_ERROR @ 3075.868624 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3075.868624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 110176312256652111528157680305051844868914765793375392723258442241387217636445 332
UVM_INFO @ 35241.388990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:342)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 40848596789785219454168747840696154786427522255685153861508315809532325714967 307
UVM_INFO @ 3993.853530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 62115286329107216669337902266458522566211360099750731617161106885742454634698 308
UVM_INFO @ 4251.010960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 14296110534095072300846036627121012160160778829872810390332979178568026986451 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 16448173881554063882131793839301769162182836334264651518395258420531871013226 343
UVM_INFO @ 4307.220680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 101419307970264392109659552934801979600577362800736938693095852683681330274637 329
UVM_INFO @ 13292.909270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 59146568666596457008185765641463869837049231301480197018169586216156160047850 215
UVM_INFO @ 2606.466843 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 45644456215879263984945691317906301419481685585176679896822220147879861181140 327
UVM_INFO @ 3777.869664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 27043958190409102645940504529308167602475653195780652370302786088017165027702 318
UVM_INFO @ 15050.693057 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 30476522354007269254392408052770118675011727697170870348274696885457838825203 329
UVM_INFO @ 14960.158315 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 109765876892611690268741970429973315298352389890116633142471356336594208557420 327
UVM_INFO @ 10680.826270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 58334933924621762021265062998448935267582772506117191863816359467590071829882 272
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 24488823466677750074162989107651404489730194130950217721761442951644178984567 319
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 7884.936489 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 19827255884604625325109653015245344706222745511892912931544306304495356104028 312
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 9199.688901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 113539634224290631573011904872205835987010465226344017284459786801131674678319 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 45830189417558956475532290473781079344614242469708225939236426962072098592976 327
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 1 test run
rom_e2e_jtag_debug_rma 95423508266736245465073728493579272675076957740597174197147806642344979914026 330
UVM_INFO @ 14289.228724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 89574046523386436153588377852618761954856556566557583269380677087864338448701 319
UVM_INFO @ 20088.377670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 68207591554229679637562840591257995406365753574399268747074930929973417849638 327
UVM_ERROR @ 6963.953338 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6963.953338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---