Simulation Results: clkmgr

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.45 %
  • code
  • 97.38 %
  • assert
  • 93.79 %
  • func
  • 83.19 %
  • line
  • 98.16 %
  • branch
  • 98.06 %
  • cond
  • 91.49 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.860s 25.002us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.010s 48.429us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.790s 40.786us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.740s 551.041us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.200s 87.057us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.970s 37.516us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.790s 40.786us 1 1 100.00
clkmgr_csr_aliasing 1.200s 87.057us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.900s 40.616us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.780s 20.453us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.710s 18.223us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.730s 48.002us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.860s 25.002us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 9.510s 2002.095us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.530s 2042.303us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 9.510s 2002.095us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 7.570s 3434.927us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.450s 151.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.710s 225.180us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.710s 225.180us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.010s 48.429us 1 1 100.00
clkmgr_csr_rw 0.790s 40.786us 1 1 100.00
clkmgr_csr_aliasing 1.200s 87.057us 1 1 100.00
clkmgr_same_csr_outstanding 0.860s 23.154us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.010s 48.429us 1 1 100.00
clkmgr_csr_rw 0.790s 40.786us 1 1 100.00
clkmgr_csr_aliasing 1.200s 87.057us 1 1 100.00
clkmgr_same_csr_outstanding 0.860s 23.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.780s 313.289us 0 1 0.00
clkmgr_tl_intg_err 2.130s 115.196us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.020s 551.666us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.020s 551.666us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.020s 551.666us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.020s 551.666us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 633.060s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.130s 115.196us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 9.510s 2002.095us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.530s 2042.303us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.020s 551.666us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.000s 83.283us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.930s 31.836us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.870s 26.327us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.910s 18.464us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.710s 38.269us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.790s 40.786us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.780s 313.289us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 40.786us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 40.786us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.780s 313.289us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.910s 2133.753us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 22.600s 3158.289us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 97963250907313309086815802329565362430714504801934686525575617285179223856910 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 87264086939649952657582659903670117315623912312504146145200643346419283946077 207
UVM_INFO @ 313288559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---