Simulation Results: csrng

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.26 %
  • code
  • 92.15 %
  • assert
  • 93.23 %
  • func
  • 73.39 %
  • block
  • 96.82 %
  • line
  • 97.55 %
  • branch
  • 92.09 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 33.172us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 40.610us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 67.451us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 18.000s 582.335us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 156.995us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 87.018us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 67.451us 1 1 100.00
csrng_csr_aliasing 5.000s 156.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 591.139us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 49.967us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 49.967us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 192.000s 5143.048us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 3.000s 17.488us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 80.468us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 181.452us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 181.452us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 40.610us 1 1 100.00
csrng_csr_rw 2.000s 67.451us 1 1 100.00
csrng_csr_aliasing 5.000s 156.995us 1 1 100.00
csrng_same_csr_outstanding 3.000s 31.899us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 40.610us 1 1 100.00
csrng_csr_rw 2.000s 67.451us 1 1 100.00
csrng_csr_aliasing 5.000s 156.995us 1 1 100.00
csrng_same_csr_outstanding 3.000s 31.899us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 322.602us 1 1 100.00
csrng_tl_intg_err 7.000s 398.282us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 3.000s 17.716us 1 1 100.00
csrng_csr_rw 2.000s 67.451us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 591.139us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 192.000s 5143.048us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
csrng_sec_cm 5.000s 322.602us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
csrng_sec_cm 5.000s 322.602us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
csrng_sec_cm 5.000s 322.602us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
csrng_sec_cm 5.000s 322.602us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
csrng_sec_cm 5.000s 322.602us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 591.139us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 192.000s 5143.048us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 591.139us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 7.000s 398.282us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
csrng_sec_cm 5.000s 322.602us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
csrng_sec_cm 5.000s 322.602us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 276.049us 1 1 100.00
csrng_err 2.000s 25.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 110.000s 7600.331us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 20467037660154265549761527030856256917830820540194507618639824501625480329998 100
UVM_INFO @ 49967268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 33980933047160924042565882367816828532775024340663133024095483712336159927111 200
UVM_INFO @ 7600331291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---