Simulation Results: edn/edn0

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.04 %
  • code
  • 76.55 %
  • assert
  • 94.79 %
  • func
  • 77.78 %
  • line
  • 96.09 %
  • branch
  • 86.61 %
  • cond
  • 82.30 %
  • toggle
  • 74.76 %
  • FSM
  • 43.01 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 25.946us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 31.910us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 25.537us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.300s 166.873us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 93.211us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.040s 24.107us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 25.537us 1 1 100.00
edn_csr_aliasing 1.150s 93.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 46.794us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 46.794us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 46.794us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.010s 21.387us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.070s 104.374us 1 1 100.00
errs 1 1 100.00
edn_err 0.830s 30.810us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 32.854us 1 1 100.00
edn_disable_auto_req_mode 1.130s 39.631us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.240s 179.846us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 49.226us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 52.630us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.950s 39.860us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.950s 39.860us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 31.910us 1 1 100.00
edn_csr_rw 0.840s 25.537us 1 1 100.00
edn_csr_aliasing 1.150s 93.211us 1 1 100.00
edn_same_csr_outstanding 0.830s 23.590us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 31.910us 1 1 100.00
edn_csr_rw 0.840s 25.537us 1 1 100.00
edn_csr_aliasing 1.150s 93.211us 1 1 100.00
edn_same_csr_outstanding 0.830s 23.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.180s 1885.887us 1 1 100.00
edn_tl_intg_err 1.400s 201.574us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 49.419us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.070s 104.374us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.180s 1885.887us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.180s 1885.887us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.180s 1885.887us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.180s 1885.887us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.070s 104.374us 1 1 100.00
edn_sec_cm 10.180s 1885.887us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.070s 104.374us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.400s 201.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 58.310s 8473.506us 1 1 100.00