Simulation Results: edn/edn1

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.50 %
  • code
  • 77.20 %
  • assert
  • 97.66 %
  • func
  • 75.63 %
  • line
  • 97.04 %
  • branch
  • 89.61 %
  • cond
  • 81.92 %
  • toggle
  • 82.22 %
  • FSM
  • 35.23 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 23.846us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 14.710us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 34.477us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.490s 561.318us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.310s 434.686us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.050s 82.712us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 34.477us 1 1 100.00
edn_csr_aliasing 1.310s 434.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.190s 93.220us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.190s 93.220us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.190s 93.220us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 21.282us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.950s 45.356us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 40.190us 1 1 100.00
disable 1 2 50.00
edn_disable 0.770s 89.949us 1 1 100.00
edn_disable_auto_req_mode 4.440s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.100s 188.411us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.710s 40.380us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 25.752us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.410s 43.657us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.410s 43.657us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 14.710us 1 1 100.00
edn_csr_rw 0.760s 34.477us 1 1 100.00
edn_csr_aliasing 1.310s 434.686us 1 1 100.00
edn_same_csr_outstanding 1.090s 43.965us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 14.710us 1 1 100.00
edn_csr_rw 0.760s 34.477us 1 1 100.00
edn_csr_aliasing 1.310s 434.686us 1 1 100.00
edn_same_csr_outstanding 1.090s 43.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.140s 160.875us 1 1 100.00
edn_tl_intg_err 1.850s 1178.403us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.850s 16.901us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.950s 45.356us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.140s 160.875us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.140s 160.875us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.140s 160.875us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.140s 160.875us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.950s 45.356us 1 1 100.00
edn_sec_cm 2.140s 160.875us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.950s 45.356us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.850s 1178.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 70.210s 4479.152us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 108352104477787654466769678148485118638848693930191431366725676665721454602671 273
UVM_INFO @ 4479152421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 31340652397512147221745015038407468363919943987504936157251570986918699094180 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---