Simulation Results: entropy_src/rng_4bits

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.40 %
  • code
  • 88.03 %
  • assert
  • 84.56 %
  • func
  • 47.62 %
  • block
  • 94.43 %
  • line
  • 97.14 %
  • branch
  • 86.53 %
  • toggle
  • 75.73 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 106.252us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 39.986us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 37.825us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 119.438us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 760.237us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 10.030us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 37.825us 1 1 100.00
entropy_src_csr_aliasing 4.000s 760.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 106.252us 1 1 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
entropy_src_fw_ov 54.000s 13143.294us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 54.000s 13143.294us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 57.000s 14247.170us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
entropy_src_intr 8.000s 1520.573us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
entropy_src_functional_alerts 4.000s 184.884us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 99.000s 14307.956us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 43.447us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 24.526us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 56.254us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 30.943us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 40.186us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 40.186us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 39.986us 1 1 100.00
entropy_src_csr_rw 1.000s 37.825us 1 1 100.00
entropy_src_csr_aliasing 4.000s 760.237us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 87.308us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 39.986us 1 1 100.00
entropy_src_csr_rw 1.000s 37.825us 1 1 100.00
entropy_src_csr_aliasing 4.000s 760.237us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 87.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 126.919us 1 1 100.00
entropy_src_tl_intg_err 4.000s 185.674us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
entropy_src_cfg_regwen 2.000s 95.312us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
entropy_src_fw_ov 54.000s 13143.294us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 43.447us 1 1 100.00
entropy_src_sec_cm 2.000s 126.919us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 43.447us 1 1 100.00
entropy_src_sec_cm 2.000s 126.919us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 58.000s 14137.717us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 43.447us 1 1 100.00
entropy_src_sec_cm 2.000s 126.919us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 43.447us 1 1 100.00
entropy_src_sec_cm 2.000s 126.919us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 43.447us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 184.884us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 185.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 57.000s 13252.284us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 5.000s 149.817us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 13985250584739934600409631525705726670805316513587615044779163396908196004120 216
UVM_INFO @ 149816557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror repcnts_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 61194573861772278394486532750437851219751638118573933807848965439411750558850 113
UVM_INFO @ 10030334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---