Simulation Results: flash_ctrl

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 93.56 %
  • assert
  • 96.94 %
  • func
  • 95.48 %
  • line
  • 95.99 %
  • branch
  • 97.19 %
  • cond
  • 93.49 %
  • toggle
  • 96.10 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 32.430s 26.982us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.490s 54.856us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 14.580s 34.560us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.360s 106.549us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 36.360s 11733.997us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 18.220s 462.374us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.640s 243.807us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.360s 106.549us 1 1 100.00
flash_ctrl_csr_aliasing 18.220s 462.374us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 10.430s 54.770us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.320s 67.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 16.510s 105.049us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 53.350s 61.776us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1116.040s 167828.536us 1 1 100.00
flash_ctrl_hw_rma_reset 572.030s 270262.596us 1 1 100.00
flash_ctrl_lcmgr_intg 12.190s 29.533us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1130.870s 320675.649us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 201.550s 2768.141us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.410s 24.418us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2415.680s 55270.878us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 101.320s 7991.684us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.390s 88.814us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.650s 70.020us 1 1 100.00
flash_ctrl_re_evict 17.000s 139.199us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 84.130s 59.847us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 84.130s 59.847us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 102.970s 12325.732us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.160s 2817.372us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 402.810s 685.771us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 300.950s 16328.124us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 346.490s 952.176us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1035.510s 2097.138us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.450s 29.970us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 141.590s 1894.071us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.700s 35.494us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.910s 51.655us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 246.760s 1615.668us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 95.270s 5935.311us 1 1 100.00
flash_ctrl_otp_reset 46.260s 131.111us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1116.040s 167828.536us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 78.700s 1245.369us 1 1 100.00
flash_ctrl_intr_wr 53.910s 12038.590us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 87.190s 5897.641us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 118.890s 50308.454us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 46.050s 9592.063us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 42.800s 1554.008us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.190s 108.570us 1 1 100.00
flash_ctrl_ro_derr 95.070s 13108.904us 1 1 100.00
flash_ctrl_rw_derr 135.160s 14415.954us 1 1 100.00
flash_ctrl_derr_detect 102.450s 3176.617us 1 1 100.00
flash_ctrl_integrity 371.900s 7394.471us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 14.500s 108.242us 1 1 100.00
flash_ctrl_ro_serr 96.690s 797.486us 1 1 100.00
flash_ctrl_rw_serr 112.440s 1625.032us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 54.740s 1841.195us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 47.650s 965.509us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 96.400s 2756.177us 1 1 100.00
flash_ctrl_write_word_sweep 8.020s 81.549us 1 1 100.00
flash_ctrl_read_word_sweep 8.230s 106.524us 1 1 100.00
flash_ctrl_ro 86.670s 4619.424us 1 1 100.00
flash_ctrl_rw 364.590s 14625.457us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.510s 407.251us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 608.660s 336003.641us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 27.960s 10063.447us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.080s 43.016us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.040s 17.710us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.240s 68.179us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.240s 68.179us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.580s 34.560us 1 1 100.00
flash_ctrl_csr_rw 8.360s 106.549us 1 1 100.00
flash_ctrl_csr_aliasing 18.220s 462.374us 1 1 100.00
flash_ctrl_same_csr_outstanding 17.180s 66.426us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.580s 34.560us 1 1 100.00
flash_ctrl_csr_rw 8.360s 106.549us 1 1 100.00
flash_ctrl_csr_aliasing 18.220s 462.374us 1 1 100.00
flash_ctrl_same_csr_outstanding 17.180s 66.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.580s 45.172us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 22.580s 45.172us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.580s 45.172us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 22.580s 45.172us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 30.300s 347.109us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1687.420s 5437.295us 1 1 100.00
flash_ctrl_tl_intg_err 215.270s 394.058us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 215.270s 394.058us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 215.270s 394.058us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.110s 901.278us 1 1 100.00
flash_ctrl_wr_intg 7.220s 181.086us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 32.430s 26.982us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 46.260s 131.111us 1 1 100.00
flash_ctrl_disable 9.700s 35.494us 1 1 100.00
flash_ctrl_sec_info_access 38.180s 6413.275us 1 1 100.00
flash_ctrl_connect 5.910s 51.655us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.730s 64.806us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.360s 106.549us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.580s 45.172us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.360s 106.549us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.580s 45.172us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.360s 106.549us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.580s 45.172us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.700s 35.494us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.110s 901.278us 1 1 100.00
flash_ctrl_access_after_disable 6.620s 21.698us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.450s 41.873us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.700s 35.494us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.160s 2817.372us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 364.590s 14625.457us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 112.440s 1625.032us 1 1 100.00
flash_ctrl_rw_derr 135.160s 14415.954us 1 1 100.00
flash_ctrl_integrity 371.900s 7394.471us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1116.040s 167828.536us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1687.420s 5437.295us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1687.420s 5437.295us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1687.420s 5437.295us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1687.420s 5437.295us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.430s 924.788us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.340s 42.265us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.420s 24.157us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1687.420s 5437.295us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1687.420s 5437.295us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1687.420s 5437.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 23.110s 262.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 166.080s 246.043us 1 1 100.00