Simulation Results: hmac

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.29 %
  • code
  • 97.76 %
  • assert
  • 97.38 %
  • func
  • 42.73 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.560s 507.078us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 151.207us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.100s 32.983us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.790s 4086.175us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.210s 613.218us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.110s 20.269us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.100s 32.983us 1 1 100.00
hmac_csr_aliasing 5.210s 613.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 47.680s 1755.757us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 40.560s 6009.152us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 233.430s 10061.391us 1 1 100.00
hmac_test_sha384_vectors 458.050s 74902.758us 1 1 100.00
hmac_test_sha512_vectors 20.900s 345.443us 1 1 100.00
hmac_test_hmac256_vectors 10.560s 990.652us 1 1 100.00
hmac_test_hmac384_vectors 11.500s 472.503us 1 1 100.00
hmac_test_hmac512_vectors 8.480s 868.452us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 2.530s 66.838us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 1115.750s 12271.278us 1 1 100.00
error 1 1 100.00
hmac_error 24.070s 788.597us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 11.470s 1246.096us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.560s 507.078us 1 1 100.00
hmac_long_msg 47.680s 1755.757us 1 1 100.00
hmac_back_pressure 40.560s 6009.152us 1 1 100.00
hmac_datapath_stress 1115.750s 12271.278us 1 1 100.00
hmac_burst_wr 2.530s 66.838us 1 1 100.00
hmac_stress_all 91.940s 17326.063us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.560s 507.078us 1 1 100.00
hmac_long_msg 47.680s 1755.757us 1 1 100.00
hmac_back_pressure 40.560s 6009.152us 1 1 100.00
hmac_datapath_stress 1115.750s 12271.278us 1 1 100.00
hmac_wipe_secret 11.470s 1246.096us 1 1 100.00
hmac_test_sha256_vectors 233.430s 10061.391us 1 1 100.00
hmac_test_sha384_vectors 458.050s 74902.758us 1 1 100.00
hmac_test_sha512_vectors 20.900s 345.443us 1 1 100.00
hmac_test_hmac256_vectors 10.560s 990.652us 1 1 100.00
hmac_test_hmac384_vectors 11.500s 472.503us 1 1 100.00
hmac_test_hmac512_vectors 8.480s 868.452us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.560s 507.078us 1 1 100.00
hmac_long_msg 47.680s 1755.757us 1 1 100.00
hmac_back_pressure 40.560s 6009.152us 1 1 100.00
hmac_datapath_stress 1115.750s 12271.278us 1 1 100.00
hmac_burst_wr 2.530s 66.838us 1 1 100.00
hmac_error 24.070s 788.597us 1 1 100.00
hmac_wipe_secret 11.470s 1246.096us 1 1 100.00
hmac_test_sha256_vectors 233.430s 10061.391us 1 1 100.00
hmac_test_sha384_vectors 458.050s 74902.758us 1 1 100.00
hmac_test_sha512_vectors 20.900s 345.443us 1 1 100.00
hmac_test_hmac256_vectors 10.560s 990.652us 1 1 100.00
hmac_test_hmac384_vectors 11.500s 472.503us 1 1 100.00
hmac_test_hmac512_vectors 8.480s 868.452us 1 1 100.00
hmac_stress_all 91.940s 17326.063us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 91.940s 17326.063us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 13.240us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 15.119us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.100s 106.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.100s 106.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 151.207us 1 1 100.00
hmac_csr_rw 1.100s 32.983us 1 1 100.00
hmac_csr_aliasing 5.210s 613.218us 1 1 100.00
hmac_same_csr_outstanding 1.070s 113.665us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 151.207us 1 1 100.00
hmac_csr_rw 1.100s 32.983us 1 1 100.00
hmac_csr_aliasing 5.210s 613.218us 1 1 100.00
hmac_same_csr_outstanding 1.070s 113.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.790s 135.190us 1 1 100.00
hmac_tl_intg_err 1.690s 108.211us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.690s 108.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.560s 507.078us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.400s 827.484us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 159.750s 10765.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.320s 733.674us 1 1 100.00