| V1 |
|
100.00% |
| V2 |
|
82.93% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_smoke | 1 | 1 | 100.00 | |||
| i2c_host_smoke | 33.050s | 5244.846us | 1 | 1 | 100.00 | |
| target_smoke | 1 | 1 | 100.00 | |||
| i2c_target_smoke | 15.130s | 910.274us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| i2c_csr_hw_reset | 0.710s | 18.487us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| i2c_csr_rw | 0.670s | 26.001us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| i2c_csr_bit_bash | 3.660s | 323.264us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| i2c_csr_aliasing | 1.500s | 649.033us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| i2c_csr_mem_rw_with_rand_reset | 0.810s | 75.768us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| i2c_csr_rw | 0.670s | 26.001us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.500s | 649.033us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_error_intr | 0 | 1 | 0.00 | |||
| i2c_host_error_intr | 0.860s | 19.363us | 0 | 1 | 0.00 | |
| host_stress_all | 0 | 1 | 0.00 | |||
| i2c_host_stress_all | 144.820s | 6954.243us | 0 | 1 | 0.00 | |
| host_maxperf | 1 | 1 | 100.00 | |||
| i2c_host_perf | 632.310s | 27014.569us | 1 | 1 | 100.00 | |
| host_override | 1 | 1 | 100.00 | |||
| i2c_host_override | 0.780s | 94.068us | 1 | 1 | 100.00 | |
| host_fifo_watermark | 1 | 1 | 100.00 | |||
| i2c_host_fifo_watermark | 94.290s | 13332.259us | 1 | 1 | 100.00 | |
| host_fifo_overflow | 1 | 1 | 100.00 | |||
| i2c_host_fifo_overflow | 26.450s | 1794.009us | 1 | 1 | 100.00 | |
| host_fifo_reset | 2 | 3 | 66.67 | |||
| i2c_host_fifo_reset_fmt | 0.850s | 161.874us | 1 | 1 | 100.00 | |
| i2c_host_fifo_fmt_empty | 7.080s | 10000.000us | 0 | 1 | 0.00 | |
| i2c_host_fifo_reset_rx | 5.280s | 165.385us | 1 | 1 | 100.00 | |
| host_fifo_full | 1 | 1 | 100.00 | |||
| i2c_host_fifo_full | 65.820s | 2185.624us | 1 | 1 | 100.00 | |
| host_timeout | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 7.680s | 2122.663us | 1 | 1 | 100.00 | |
| i2c_host_mode_toggle | 0 | 1 | 0.00 | |||
| i2c_host_mode_toggle | 1.170s | 50.090us | 0 | 1 | 0.00 | |
| target_glitch | 0 | 1 | 0.00 | |||
| i2c_target_glitch | 1.930s | 525.290us | 0 | 1 | 0.00 | |
| target_stress_all | 1 | 1 | 100.00 | |||
| i2c_target_stress_all | 52.970s | 24990.112us | 1 | 1 | 100.00 | |
| target_maxperf | 1 | 1 | 100.00 | |||
| i2c_target_perf | 2.890s | 4940.919us | 1 | 1 | 100.00 | |
| target_fifo_empty | 2 | 2 | 100.00 | |||
| i2c_target_stress_rd | 9.480s | 816.669us | 1 | 1 | 100.00 | |
| i2c_target_intr_smoke | 2.810s | 716.282us | 1 | 1 | 100.00 | |
| target_fifo_reset | 2 | 2 | 100.00 | |||
| i2c_target_fifo_reset_acq | 1.340s | 209.347us | 1 | 1 | 100.00 | |
| i2c_target_fifo_reset_tx | 1.430s | 296.953us | 1 | 1 | 100.00 | |
| target_fifo_full | 3 | 3 | 100.00 | |||
| i2c_target_stress_wr | 14.200s | 12627.174us | 1 | 1 | 100.00 | |
| i2c_target_stress_rd | 9.480s | 816.669us | 1 | 1 | 100.00 | |
| i2c_target_intr_stress_wr | 103.340s | 12284.378us | 1 | 1 | 100.00 | |
| target_timeout | 1 | 1 | 100.00 | |||
| i2c_target_timeout | 4.510s | 2522.215us | 1 | 1 | 100.00 | |
| target_clock_stretch | 1 | 1 | 100.00 | |||
| i2c_target_stretch | 22.370s | 2039.376us | 1 | 1 | 100.00 | |
| bad_address | 1 | 1 | 100.00 | |||
| i2c_target_bad_addr | 5.630s | 14314.233us | 1 | 1 | 100.00 | |
| target_mode_glitch | 0 | 1 | 0.00 | |||
| i2c_target_hrst | 14.500s | 10078.719us | 0 | 1 | 0.00 | |
| target_fifo_watermark | 2 | 2 | 100.00 | |||
| i2c_target_fifo_watermarks_acq | 2.730s | 1892.255us | 1 | 1 | 100.00 | |
| i2c_target_fifo_watermarks_tx | 1.130s | 601.966us | 1 | 1 | 100.00 | |
| host_mode_config_perf | 2 | 2 | 100.00 | |||
| i2c_host_perf | 632.310s | 27014.569us | 1 | 1 | 100.00 | |
| i2c_host_perf_precise | 94.590s | 23656.112us | 1 | 1 | 100.00 | |
| host_mode_clock_stretching | 1 | 1 | 100.00 | |||
| i2c_host_stretch_timeout | 7.680s | 2122.663us | 1 | 1 | 100.00 | |
| target_mode_tx_stretch_ctrl | 1 | 1 | 100.00 | |||
| i2c_target_tx_stretch_ctrl | 13.720s | 1728.758us | 1 | 1 | 100.00 | |
| target_mode_nack_generation | 2 | 3 | 66.67 | |||
| i2c_target_nack_acqfull | 2.200s | 2236.481us | 1 | 1 | 100.00 | |
| i2c_target_nack_acqfull_addr | 2.480s | 2117.917us | 1 | 1 | 100.00 | |
| i2c_target_nack_txstretch | 1.120s | 835.298us | 0 | 1 | 0.00 | |
| host_mode_halt_on_nak | 1 | 1 | 100.00 | |||
| i2c_host_may_nack | 9.880s | 3801.192us | 1 | 1 | 100.00 | |
| target_mode_smbus_maxlen | 1 | 1 | 100.00 | |||
| i2c_target_smbus_maxlen | 1.370s | 835.070us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| i2c_alert_test | 0.800s | 55.397us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| i2c_intr_test | 0.900s | 43.027us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| i2c_tl_errors | 2.040s | 222.903us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| i2c_tl_errors | 2.040s | 222.903us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| i2c_csr_hw_reset | 0.710s | 18.487us | 1 | 1 | 100.00 | |
| i2c_csr_rw | 0.670s | 26.001us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.500s | 649.033us | 1 | 1 | 100.00 | |
| i2c_same_csr_outstanding | 1.190s | 61.071us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| i2c_csr_hw_reset | 0.710s | 18.487us | 1 | 1 | 100.00 | |
| i2c_csr_rw | 0.670s | 26.001us | 1 | 1 | 100.00 | |
| i2c_csr_aliasing | 1.500s | 649.033us | 1 | 1 | 100.00 | |
| i2c_same_csr_outstanding | 1.190s | 61.071us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| i2c_tl_intg_err | 1.500s | 290.918us | 1 | 1 | 100.00 | |
| i2c_sec_cm | 1.150s | 432.436us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| i2c_tl_intg_err | 1.500s | 290.918us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| host_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_host_stress_all_with_rand_reset | 4.080s | 145.385us | 0 | 1 | 0.00 | |
| target_error_intr | 0 | 1 | 0.00 | |||
| i2c_target_unexp_stop | 1.230s | 416.990us | 0 | 1 | 0.00 | |
| target_stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| i2c_target_stress_all_with_rand_reset | 8.340s | 10665.885us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between | 2 test runs | |||
| i2c_host_error_intr | 68115231367581454489558923671752592618247406174682632894566545634688527882931 | 96 |
UVM_INFO @ 19363197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_host_stress_all | 29598512600035906584566510455428680118777136601295641359864322313428837637645 | 106 |
UVM_INFO @ 6954242661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 2 test runs | |||
| i2c_host_stress_all_with_rand_reset | 27085453468130040910323452483516097657728109193570018949459390660728083680050 | 84 |
UVM_INFO @ 145384613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| i2c_target_stress_all_with_rand_reset | 78408711587946369495648683797672347646284366556327796227782947136638767375256 | 87 |
UVM_INFO @ 10665885239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| i2c_host_fifo_fmt_empty | 11390234539354569621626980386921327427283345923355087837468238497440875783356 | 78 |
UVM_INFO @ 10000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between | 1 test run | |||
| i2c_target_glitch | 69258571411734864464783333242957635452702805643798971436070625312943869907066 | 84 |
UVM_INFO @ 525290209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) | 1 test run | |||
| i2c_target_unexp_stop | 4128675349630975573092216141477819160956689880036689006251341345735943321054 | 78 |
UVM_INFO @ 416989774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! | 1 test run | |||
| i2c_target_hrst | 37950195114218922819621365818123748778748314593593105395875121997175223478572 | 79 |
UVM_INFO @ 10078718938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead | 1 test run | |||
| i2c_host_mode_toggle | 5507655794519116550232335635116823852442321038892289997662913013573519682236 | 87 |
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * | 1 test run | |||
| i2c_target_nack_txstretch | 66766664588459562345915924879674414540084716675861166148067905459689505600288 | 78 |
UVM_INFO @ 835298024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|